amd/amdgpu/amdgpu_ctx.c

138 static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip)
147 	switch (hw_ip) {
161 	hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM);
162 	if (adev->gpu_sched[hw_ip][hw_prio].num_scheds == 0)
203 static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip,
221 	entity->hw_ip = hw_ip;
223 	hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip);
226 	hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM);
229 		scheds = adev->gpu_sched[hw_ip][hw_prio].sched;
230 		num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds;
235 		r = amdgpu_xcp_select_scheds(adev, hw_ip, hw_prio, fpriv,
242 	if (hw_ip == AMDGPU_HW_IP_VCN_ENC ||
243 	    hw_ip == AMDGPU_HW_IP_VCN_DEC ||
244 	    hw_ip == AMDGPU_HW_IP_UVD_ENC ||
245 	    hw_ip == AMDGPU_HW_IP_UVD) {
257 	if (cmpxchg(&ctx->entities[hw_ip][ring], NULL, entity))
433 int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,
439 	if (hw_ip >= AMDGPU_HW_IP_NUM) {
440 		DRM_ERROR("unknown HW IP type: %d\n", hw_ip);
450 	if (ring >= amdgpu_ctx_num_entities[hw_ip]) {
451 		DRM_DEBUG("invalid ring: %d %d\n", hw_ip, ring);
455 	if (ctx->entities[hw_ip][ring] == NULL) {
456 		r = amdgpu_ctx_init_entity(ctx, hw_ip, ring);
461 	ctx_entity = &ctx->entities[hw_ip][ring]->entity;
769 		     &ctx->mgr->time_spend[centity->hw_ip]);
806 					   int hw_ip,
819 	if (hw_ip == AMDGPU_HW_IP_COMPUTE || hw_ip == AMDGPU_HW_IP_GFX) {
820 		hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip);
822 		scheds = adev->gpu_sched[hw_ip][hw_prio].sched;
823 		num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds;
964 	unsigned int hw_ip, i;
973 	for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) {
974 		uint64_t ns = atomic64_read(&mgr->time_spend[hw_ip]);
976 		usage[hw_ip] = ns_to_ktime(ns);
980 		for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) {
981 			for (i = 0; i < amdgpu_ctx_num_entities[hw_ip]; ++i) {
985 				centity = ctx->entities[hw_ip][i];
989 				usage[hw_ip] = ktime_add(usage[hw_ip], spend);