dev/pci/cs4280.c

161 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x))
430 	BA1WRITE4(sc, CS4280_CSRC, tmp1);
433 	BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy));
444 	BA1WRITE4(sc, CS4280_CCI, tmp1);
446 	BA1WRITE4(sc, CS4280_CCI, cci);
451 	BA1WRITE4(sc, CS4280_CD, tmp1);
453 	BA1WRITE4(sc, CS4280_CPI, cpi);
457 	BA1WRITE4(sc, CS4280_CGL, tmp1);
459 	BA1WRITE4(sc, CS4280_CNT, cnt);
463 	BA1WRITE4(sc, CS4280_CGC, tmp1);
502 	BA1WRITE4(sc, CS4280_PSRC,
506 	BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py));
508 	BA1WRITE4(sc, CS4280_PPI, ppi);
659 		BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE);
675 		BA1WRITE4(sc, CS4280_PFIE, mem);
684 		BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE);
737 		BA1WRITE4(sc, CS4280_CIE, mem);
809 		BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr)));
959 	BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP);
962 	BA1WRITE4(sc, CS4280_SPCR, 0);
964 	BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN);
1082 	BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK);
1098 	BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK);
1252 	BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK);
1258 	BA1WRITE4(sc, CS4280_PDTC, pdtc);
1293 	BA1WRITE4(sc, CS4280_PBA, DMAADDR(p));
1310 	BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE);
1316 	BA1WRITE4(sc, CS4280_PCTL, pctl);
1358 	BA1WRITE4(sc, CS4280_CCTL, cctl);
1376 	BA1WRITE4(sc, CS4280_CBA, DMAADDR(p));
1380 	BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE);
1386 	BA1WRITE4(sc, CS4280_CCTL, cctl);
1515 	BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV);
1516 	BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
1539 	BA1WRITE4(sc, CS4280_PVOL, 0x80008000);
1540 	BA1WRITE4(sc, CS4280_CVOL, 0x80008000);
1548 	BA1WRITE4(sc, CS4280_PFIE, mem);
1552 	BA1WRITE4(sc, CS4280_CIE, mem);