dev/mii/rgephy.c

114 	struct mii_softc *sc = (struct mii_softc *)self;
122 	sc->mii_inst = mii->mii_instance;
123 	sc->mii_phy = ma->mii_phyno;
124 	sc->mii_funcs = &rgephy_funcs;
125 	sc->mii_model = MII_MODEL(ma->mii_id2);
126 	sc->mii_rev = MII_REV(ma->mii_id2);
127 	sc->mii_pdata = mii;
128 	sc->mii_flags = ma->mii_flags;
129 	sc->mii_anegticks = MII_ANEGTICKS_GIGE;
131 	sc->mii_flags |= MIIF_NOISOLATE;
133 	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
135 	if (sc->mii_capabilities & BMSR_EXTSTAT)
136 		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
137 	if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
138 	    (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
139 		mii_phy_add_media(sc);
141 	if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8211FVD ||
142 	    (sc->mii_model == MII_MODEL_xxREALTEK_RTL8169S &&
143 	     sc->mii_rev == RGEPHY_8211F))
144 		rgephy_init_rtl8211f(sc);
146 	PHY_RESET(sc);
150 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
156 	devname = sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name;
163 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
172 		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
173 			reg = PHY_READ(sc, MII_BMCR);
174 			PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
184 		PHY_RESET(sc);	/* XXX hardware bug work-around */
186 		anar = PHY_READ(sc, MII_ANAR);
191 			(void) rgephy_mii_phy_auto(sc);
204 			rgephy_loop(sc);
221 			PHY_WRITE(sc, MII_100T2CR, gig);
222 			PHY_WRITE(sc, MII_BMCR, speed | BMCR_AUTOEN |
224 			PHY_WRITE(sc, MII_ANAR, anar);
228 			PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
240 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
261 			reg = PHY_READ(sc, RL_GMEDIASTAT);
263 				sc->mii_ticks = 0;
266 		} else if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8211FVD ||
267 		    (sc->mii_model == MII_MODEL_xxREALTEK_RTL8169S &&
268 		     sc->mii_rev == RGEPHY_8211F)) {
269 			reg = PHY_READ(sc, RGEPHY_F_SR);
271 				sc->mii_ticks = 0;
274 			reg = PHY_READ(sc, RGEPHY_SR);
276 				sc->mii_ticks = 0;
284 		if (++sc->mii_ticks <= sc->mii_anegticks)
287 		sc->mii_ticks = 0;
288 		rgephy_mii_phy_auto(sc);
293 	mii_phy_status(sc);
300 	if (sc->mii_media_active != mii->mii_media_active ||
301 	    sc->mii_media_status != mii->mii_media_status ||
303 		rgephy_load_dspcode(sc);
306 	mii_phy_update(sc, cmd);
312 rgephy_status(struct mii_softc *sc)
314 	struct mii_data *mii = sc->mii_pdata;
318 	devname = sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name;
324 		bmsr = PHY_READ(sc, RL_GMEDIASTAT);
327 	} else if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8211FVD ||
328 	    (sc->mii_model == MII_MODEL_xxREALTEK_RTL8169S &&
329 	     sc->mii_rev == RGEPHY_8211F)) {
330 		bmsr = PHY_READ(sc, RGEPHY_F_SR);
334 		bmsr = PHY_READ(sc, RGEPHY_SR);
339 	bmsr = PHY_READ(sc, MII_BMSR);
341 	bmcr = PHY_READ(sc, MII_BMCR);
355 		bmsr = PHY_READ(sc, RL_GMEDIASTAT);
364 			mii->mii_media_active |= mii_phy_flowstatus(sc) |
368 	} else if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8211FVD ||
369 	    (sc->mii_model == MII_MODEL_xxREALTEK_RTL8169S &&
370 	     sc->mii_rev == RGEPHY_8211F)) {
371 		bmsr = PHY_READ(sc, RGEPHY_F_SR);
380 			mii->mii_media_active |= mii_phy_flowstatus(sc) |
385 		bmsr = PHY_READ(sc, RGEPHY_SR);
394 			mii->mii_media_active |= mii_phy_flowstatus(sc) |
400 	gtsr = PHY_READ(sc, MII_100T2SR);
408 rgephy_mii_phy_auto(struct mii_softc *sc)
412 	rgephy_loop(sc);
413 	PHY_RESET(sc);
415 	anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
416 	if (sc->mii_flags & MIIF_DOPAUSE)
419 	PHY_WRITE(sc, MII_ANAR, anar);
421 	PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX);
423 	PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
430 rgephy_loop(struct mii_softc *sc)
435 	if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8169S &&
436 	    sc->mii_rev < 2) {
437 		PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN);
442 		bmsr = PHY_READ(sc, MII_BMSR);
450 rgephy_init_rtl8211f(struct mii_softc *sc)
452 	if (sc->mii_flags & MIIF_SETDELAY) {
456 		page = PHY_READ(sc, RGEPHY_PS);
457 		PHY_WRITE(sc, RGEPHY_PS, RGEPHY_PS_PAGE_MII);
459 		val = PHY_READ(sc, RGEPHY_MIICR1);
460 		if (sc->mii_flags & MIIF_TXID)
464 		PHY_WRITE(sc, RGEPHY_MIICR1, val);
466 		val = PHY_READ(sc, RGEPHY_MIICR2);
467 		if (sc->mii_flags & MIIF_RXID)
471 		PHY_WRITE(sc, RGEPHY_MIICR2, val);
474 		PHY_WRITE(sc, RGEPHY_PS, page);
491 rgephy_load_dspcode(struct mii_softc *sc)
495 	if (sc->mii_model != MII_MODEL_xxREALTEK_RTL8169S ||
496 	    sc->mii_rev > 1)
499 	PHY_WRITE(sc, 31, 0x0001);
500 	PHY_WRITE(sc, 21, 0x1000);
501 	PHY_WRITE(sc, 24, 0x65C7);
502 	PHY_CLRBIT(sc, 4, 0x0800);
503 	val = PHY_READ(sc, 4) & 0xFFF;
504 	PHY_WRITE(sc, 4, val);
505 	PHY_WRITE(sc, 3, 0x00A1);
506 	PHY_WRITE(sc, 2, 0x0008);
507 	PHY_WRITE(sc, 1, 0x1020);
508 	PHY_WRITE(sc, 0, 0x1000);
509 	PHY_SETBIT(sc, 4, 0x0800);
510 	PHY_CLRBIT(sc, 4, 0x0800);
511 	val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
512 	PHY_WRITE(sc, 4, val);
513 	PHY_WRITE(sc, 3, 0xFF41);
514 	PHY_WRITE(sc, 2, 0xDE60);
515 	PHY_WRITE(sc, 1, 0x0140);
516 	PHY_WRITE(sc, 0, 0x0077);
517 	val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
518 	PHY_WRITE(sc, 4, val);
519 	PHY_WRITE(sc, 3, 0xDF01);
520 	PHY_WRITE(sc, 2, 0xDF20);
521 	PHY_WRITE(sc, 1, 0xFF95);
522 	PHY_WRITE(sc, 0, 0xFA00);
523 	val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
524 	PHY_WRITE(sc, 4, val);
525 	PHY_WRITE(sc, 3, 0xFF41);
526 	PHY_WRITE(sc, 2, 0xDE20);
527 	PHY_WRITE(sc, 1, 0x0140);
528 	PHY_WRITE(sc, 0, 0x00BB);
529 	val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
530 	PHY_WRITE(sc, 4, val);
531 	PHY_WRITE(sc, 3, 0xDF01);
532 	PHY_WRITE(sc, 2, 0xDF20);
533 	PHY_WRITE(sc, 1, 0xFF95);
534 	PHY_WRITE(sc, 0, 0xBF00);
535 	PHY_SETBIT(sc, 4, 0x0800);
536 	PHY_CLRBIT(sc, 4, 0x0800);
537 	PHY_WRITE(sc, 31, 0x0000);
543 rgephy_reset(struct mii_softc *sc)
545 	mii_phy_reset(sc);
547 	rgephy_load_dspcode(sc);