dev/ic/rt2661.c

934 			RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
1333 	RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16);
1335 	RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7);
1336 	RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18);
1337 	RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20);
1347 	RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
1365 	RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
1366 	RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
1369 	RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1);
1370 	RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2);
1409 	RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
1410 	RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
1677 	RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT);
1892 	RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1);
2061 	RAL_WRITE(sc, RT2661_PHY_CSR3, tmp);
2083 	RAL_WRITE(sc, RT2661_PHY_CSR3, val);
2114 	RAL_WRITE(sc, RT2661_PHY_CSR4, tmp);
2128 	RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
2131 	RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd);
2149 	RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2155 	RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2175 	RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
2189 	RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
2200 		RAL_WRITE(sc, RT2661_TXRX_CSR5, 0x3);
2203 		RAL_WRITE(sc, RT2661_TXRX_CSR5, 0x150);
2206 		RAL_WRITE(sc, RT2661_TXRX_CSR5, 0xf);
2254 	RAL_WRITE(sc, RT2661_PHY_CSR0, tmp);
2341 	RAL_WRITE(sc, RT2661_MAC_CSR4, tmp);
2344 	RAL_WRITE(sc, RT2661_MAC_CSR5, tmp);
2353 	RAL_WRITE(sc, RT2661_MAC_CSR2, tmp);
2356 	RAL_WRITE(sc, RT2661_MAC_CSR3, tmp);
2371 	RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2407 	RAL_WRITE(sc, RT2661_MAC_CSR9, tmp);
2573 	RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr);
2574 	RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr);
2575 	RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr);
2576 	RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr);
2579 	RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr);
2582 	RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr);
2585 	RAL_WRITE(sc, RT2661_TX_RING_CSR0,
2591 	RAL_WRITE(sc, RT2661_TX_RING_CSR1,
2597 	RAL_WRITE(sc, RT2661_RX_RING_CSR,
2603 	RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa);
2606 	RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f);
2609 	RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2);
2613 		RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
2619 	RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2620 	RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2660 	RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2666 	RAL_WRITE(sc, RT2661_MAC_CSR1, 4);
2669 	RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2672 	RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
2673 	RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
2676 	RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1);
2706 	RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16);
2710 	RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2713 	RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2714 	RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2717 	RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
2718 	RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
2721 	RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2722 	RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff);
2745 	RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2748 	RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0);
2749 	RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
2750 	RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0);
2753 	RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL);
2755 	RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2758 	RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0);
2848 	RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2870 	RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2966 		RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8);
2981 	RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp);