dev/ic/imxiic.c

62 #define HREAD1(sc, reg)							\
63 	imxiic_read_1((sc), (reg))
64 #define HWRITE1(sc, reg, val)						\
65 	imxiic_write_1((sc), (reg), (val))
66 #define HSET1(sc, reg, bits)						\
67 	HWRITE1((sc), (reg), HREAD1((sc), (reg)) | (bits))
68 #define HCLR1(sc, reg, bits)						\
69 	HWRITE1((sc), (reg), HREAD1((sc), (reg)) & ~(bits))
76 imxiic_enable(struct imxiic_softc *sc, int on)
82 	if (sc->sc_type == I2C_TYPE_VF610)
83 		HWRITE1(sc, I2C_I2SR, I2C_I2SR_IAL | I2C_I2SR_IIF);
85 		HWRITE1(sc, I2C_I2SR, 0);
88 	if (sc->sc_type == I2C_TYPE_VF610)
91 		HWRITE1(sc, I2C_I2CR, I2C_I2CR_IEN);
93 		HWRITE1(sc, I2C_I2CR, 0);
97 imxiic_clear_iodone(struct imxiic_softc *sc)
103 	if (sc->sc_type == I2C_TYPE_VF610)
104 		HWRITE1(sc, I2C_I2SR, I2C_I2SR_IIF);
106 		HCLR1(sc, I2C_I2SR, I2C_I2SR_IIF);
110 imxiic_setspeed(struct imxiic_softc *sc, u_int speed)
112 	if (!sc->frequency) {
116 		div = (sc->sc_clkrate + speed - 1) / speed;
117 		if (div < sc->sc_clk_div[0].div)
119 		else if (div > sc->sc_clk_div[sc->sc_clk_ndiv - 1].div)
120 			i = sc->sc_clk_ndiv - 1;
122 			for (i = 0; sc->sc_clk_div[i].div < div; i++)
125 		sc->frequency = sc->sc_clk_div[i].val;
128 	HWRITE1(sc, I2C_IFDR, sc->frequency);
132 imxiic_wait_state(struct imxiic_softc *sc, uint32_t mask, uint32_t value)
137 		if (((state = HREAD1(sc, I2C_I2SR)) & mask) == value)
145 imxiic_read(struct imxiic_softc *sc, int addr, const void *cmd, int cmdlen,
151 		if (imxiic_write(sc, addr, cmd, cmdlen, NULL, 0))
154 		HSET1(sc, I2C_I2CR, I2C_I2CR_RSTA);
156 		if (imxiic_wait_state(sc, I2C_I2SR_IBB, I2C_I2SR_IBB))
160 	imxiic_clear_iodone(sc);
161 	HWRITE1(sc, I2C_I2DR, (addr << 1) | 1);
163 	if (imxiic_wait_state(sc, I2C_I2SR_IIF, I2C_I2SR_IIF))
165 	imxiic_clear_iodone(sc);
166 	if (HREAD1(sc, I2C_I2SR) & I2C_I2SR_RXAK)
169 	HCLR1(sc, I2C_I2CR, I2C_I2CR_MTX);
171 		HCLR1(sc, I2C_I2CR, I2C_I2CR_TXAK);
174 	HREAD1(sc, I2C_I2DR);
177 		if (imxiic_wait_state(sc, I2C_I2SR_IIF, I2C_I2SR_IIF))
179 		imxiic_clear_iodone(sc);
182 			HCLR1(sc, I2C_I2CR, I2C_I2CR_MSTA | I2C_I2CR_MTX);
183 			imxiic_wait_state(sc, I2C_I2SR_IBB, 0);
184 			sc->stopped = 1;
186 			HSET1(sc, I2C_I2CR, I2C_I2CR_TXAK);
188 		((uint8_t*)data)[i] = HREAD1(sc, I2C_I2DR);
195 imxiic_write(struct imxiic_softc *sc, int addr, const void *cmd, int cmdlen,
200 	imxiic_clear_iodone(sc);
201 	HWRITE1(sc, I2C_I2DR, addr << 1);
203 	if (imxiic_wait_state(sc, I2C_I2SR_IIF, I2C_I2SR_IIF))
205 	imxiic_clear_iodone(sc);
206 	if (HREAD1(sc, I2C_I2SR) & I2C_I2SR_RXAK)
210 		HWRITE1(sc, I2C_I2DR, ((uint8_t*)cmd)[i]);
211 		if (imxiic_wait_state(sc, I2C_I2SR_IIF, I2C_I2SR_IIF))
213 		imxiic_clear_iodone(sc);
214 		if (HREAD1(sc, I2C_I2SR) & I2C_I2SR_RXAK)
219 		HWRITE1(sc, I2C_I2DR, ((uint8_t*)data)[i]);
220 		if (imxiic_wait_state(sc, I2C_I2SR_IIF, I2C_I2SR_IIF))
222 		imxiic_clear_iodone(sc);
223 		if (HREAD1(sc, I2C_I2SR) & I2C_I2SR_RXAK)
232 	struct imxiic_softc *sc = cookie;
234 	rw_enter(&sc->sc_buslock, RW_WRITE);
237 	imxiic_setspeed(sc, sc->sc_bitrate);
240 	imxiic_enable(sc, 1);
251 	struct imxiic_softc *sc = cookie;
253 	imxiic_enable(sc, 0);
255 	rw_exit(&sc->sc_buslock);
262 	struct imxiic_softc *sc = cookie;
269 	HSET1(sc, I2C_I2CR, I2C_I2CR_MSTA);
271 	if (imxiic_wait_state(sc, I2C_I2SR_IBB, I2C_I2SR_IBB)) {
276 	sc->stopped = 0;
278 	HSET1(sc, I2C_I2CR, I2C_I2CR_IIEN | I2C_I2CR_MTX | I2C_I2CR_TXAK);
281 		ret = imxiic_read(sc, addr, cmdbuf, cmdlen, buf, len);
283 		ret = imxiic_write(sc, addr, cmdbuf, cmdlen, buf, len);
287 	if (!sc->stopped) {
288 		HCLR1(sc, I2C_I2CR, I2C_I2CR_MSTA | I2C_I2CR_MTX);
289 		imxiic_wait_state(sc, I2C_I2SR_IBB, 0);
290 		sc->stopped = 1;
297 imxiic_read_1(struct imxiic_softc *sc, int reg)
299 	reg <<= sc->sc_reg_shift;
301 	return bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg);
305 imxiic_write_1(struct imxiic_softc *sc, int reg, uint8_t val)
307 	reg <<= sc->sc_reg_shift;
309 	bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val);