dev/ic/ar5xxx.c

313 	 * Calculate the transmission time by operation (PHY) mode
318 		 * CCK / DS mode (802.11b)
369     u_int max_channels, u_int *channels_size, u_int16_t mode,
385 	 * In debugging mode, enable all channels supported by the chipset
427 	 * and mode. 5GHz...
672 ar5k_eeprom_bin2freq(struct ath_hal *hal, u_int16_t bin, u_int mode)
679 	if (mode == AR5K_EEPROM_MODE_11A) {
697 ar5k_eeprom_read_ants(struct ath_hal *hal, u_int32_t *offset, u_int mode)
705 	ee->ee_switch_settling[mode]	= (val >> 8) & 0x7f;
706 	ee->ee_ant_tx_rx[mode]		= (val >> 2) & 0x3f;
707 	ee->ee_ant_control[mode][i]	= (val << 4) & 0x3f;
710 	ee->ee_ant_control[mode][i++]	|= (val >> 12) & 0xf;
711 	ee->ee_ant_control[mode][i++]	= (val >> 6) & 0x3f;
712 	ee->ee_ant_control[mode][i++]	= val & 0x3f;
715 	ee->ee_ant_control[mode][i++]	= (val >> 10) & 0x3f;
716 	ee->ee_ant_control[mode][i++]	= (val >> 4) & 0x3f;
717 	ee->ee_ant_control[mode][i]	= (val << 2) & 0x3f;
720 	ee->ee_ant_control[mode][i++]	|= (val >> 14) & 0x3;
721 	ee->ee_ant_control[mode][i++]	= (val >> 8) & 0x3f;
722 	ee->ee_ant_control[mode][i++]	= (val >> 2) & 0x3f;
723 	ee->ee_ant_control[mode][i]	= (val << 4) & 0x3f;
726 	ee->ee_ant_control[mode][i++]	|= (val >> 12) & 0xf;
727 	ee->ee_ant_control[mode][i++]	= (val >> 6) & 0x3f;
728 	ee->ee_ant_control[mode][i++]	= val & 0x3f;
731 	hal->ah_antenna[mode][0] =
732 	    (ee->ee_ant_control[mode][0] << 4) | 0x1;
733 	hal->ah_antenna[mode][HAL_ANT_FIXED_A] =
734 	    ee->ee_ant_control[mode][1] |
735 	    (ee->ee_ant_control[mode][2] << 6) |
736 	    (ee->ee_ant_control[mode][3] << 12) |
737 	    (ee->ee_ant_control[mode][4] << 18) |
738 	    (ee->ee_ant_control[mode][5] << 24);
739 	hal->ah_antenna[mode][HAL_ANT_FIXED_B] =
740 	    ee->ee_ant_control[mode][6] |
741 	    (ee->ee_ant_control[mode][7] << 6) |
742 	    (ee->ee_ant_control[mode][8] << 12) |
743 	    (ee->ee_ant_control[mode][9] << 18) |
744 	    (ee->ee_ant_control[mode][10] << 24);
753 ar5k_eeprom_read_modes(struct ath_hal *hal, u_int32_t *offset, u_int mode)
761 	ee->ee_tx_end2xlna_enable[mode]	= (val >> 8) & 0xff;
762 	ee->ee_thr_62[mode]		= val & 0xff;
765 		ee->ee_thr_62[mode] =
766 		    mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
769 	ee->ee_tx_end2xpa_disable[mode]	= (val >> 8) & 0xff;
770 	ee->ee_tx_frm2xpa_enable[mode]	= val & 0xff;
773 	ee->ee_pga_desired_size[mode]	= (val >> 8) & 0xff;
776 		ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
778 		ee->ee_noise_floor_thr[mode] = val & 0xff;
781 		ee->ee_noise_floor_thr[mode] =
782 		    mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
785 	ee->ee_xlna_gain[mode]		= (val >> 5) & 0xff;
786 	ee->ee_x_gain[mode]		= (val >> 1) & 0xf;
787 	ee->ee_xpd[mode]		= val & 0x1;
790 		ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
794 		ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
796 		if (mode == AR5K_EEPROM_MODE_11A)
797 			ee->ee_xr_power[mode] = val & 0x3f;
799 			ee->ee_ob[mode][0] = val & 0x7;
800 			ee->ee_db[mode][0] = (val >> 3) & 0x7;
805 		ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
808 		ee->ee_i_gain[mode] = (val >> 13) & 0x7;
811 		ee->ee_i_gain[mode] |= (val << 3) & 0x38;
813 		if (mode == AR5K_EEPROM_MODE_11G)
818 	    mode == AR5K_EEPROM_MODE_11A) {
819 		ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
820 		ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
824 	    mode == AR5K_EEPROM_MODE_11G)
840 	u_int mode;
908 	mode = AR5K_EEPROM_MODE_11A;
912 	if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0)
916 	ee->ee_adc_desired_size[mode]	= (int8_t)((val >> 8) & 0xff);
917 	ee->ee_ob[mode][3]		= (val >> 5) & 0x7;
918 	ee->ee_db[mode][3]		= (val >> 2) & 0x7;
919 	ee->ee_ob[mode][2]		= (val << 1) & 0x7;
922 	ee->ee_ob[mode][2]		|= (val >> 15) & 0x1;
923 	ee->ee_db[mode][2]		= (val >> 12) & 0x7;
924 	ee->ee_ob[mode][1]		= (val >> 9) & 0x7;
925 	ee->ee_db[mode][1]		= (val >> 6) & 0x7;
926 	ee->ee_ob[mode][0]		= (val >> 3) & 0x7;
927 	ee->ee_db[mode][0]		= val & 0x7;
929 	if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0)
934 		ee->ee_margin_tx_rx[mode] = val & 0x3f;
940 	mode = AR5K_EEPROM_MODE_11B;
943 	if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0)
947 	ee->ee_adc_desired_size[mode]	= (int8_t)((val >> 8) & 0xff);
948 	ee->ee_ob[mode][1]		= (val >> 4) & 0x7;
949 	ee->ee_db[mode][1]		= val & 0x7;
951 	if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0)
956 		ee->ee_cal_pier[mode][0] =
957 		    ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
958 		ee->ee_cal_pier[mode][1] =
959 		    ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
962 		ee->ee_cal_pier[mode][2] =
963 		    ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
967 		ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
973 	mode = AR5K_EEPROM_MODE_11G;
976 	if ((ret = ar5k_eeprom_read_ants(hal, &offset, mode)) != 0)
980 	ee->ee_adc_desired_size[mode]	= (int8_t)((val >> 8) & 0xff);
981 	ee->ee_ob[mode][1]		= (val >> 4) & 0x7;
982 	ee->ee_db[mode][1]		= val & 0x7;
984 	if ((ret = ar5k_eeprom_read_modes(hal, &offset, mode)) != 0)
989 		ee->ee_cal_pier[mode][0] =
990 		    ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
991 		ee->ee_cal_pier[mode][1] =
992 		    ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
995 		ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
998 		ee->ee_cal_pier[mode][2] =
999 		    ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
1002 			ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
1006 		ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
1007 		ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
1453 ar5k_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
1495 	ret = (func)(hal, channel, mode);
1504 ar5k_ar5111_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
1512 	AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
1529 		rf[i] = ar5111_rf[i].rf_value[mode];
1600 ar5k_ar5112_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
1609 	AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
1634 		rf[i] = rf_ini[i].rf_value[mode];
1696 ar5k_arxxxx_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
1703 	AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
1717 		if (mode == AR5K_INI_VAL_11B)
1718 			mode = AR5K_INI_VAL_11G;
1738 		rf[i] = rf_ini[i].rf_value[mode];
1862     size_t n, u_int mode)
1869 		    ini[i].mode_value[mode]);