dev/fdt/rkpwm.c

44 #define HREAD4(sc, reg)							\
45 	(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
46 #define HWRITE4(sc, reg, val)						\
47 	bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
48 #define HSET4(sc, reg, bits)						\
49 	HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
50 #define HCLR4(sc, reg, bits)						\
51 	HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
88 	struct rkpwm_softc *sc = (struct rkpwm_softc *)self;
96 	sc->sc_clkin = clock_get_frequency(faa->fa_node, NULL);
97 	if (sc->sc_clkin == 0) {
102 	sc->sc_iot = faa->fa_iot;
103 	if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
104 	    faa->fa_reg[0].size, 0, &sc->sc_ioh)) {
116 	sc->sc_pd.pd_node = faa->fa_node;
117 	sc->sc_pd.pd_cookie = sc;
118 	sc->sc_pd.pd_get_state = rkpwm_get_state;
119 	sc->sc_pd.pd_set_state = rkpwm_set_state;
121 	pwm_register(&sc->sc_pd);
127 	struct rkpwm_softc *sc = cookie;
134 	rate = sc->sc_clkin;
135 	cycles = HREAD4(sc, PWM_V2_PERIOD);
136 	act_cycles = HREAD4(sc, PWM_V2_DUTY);
141 	if (HREAD4(sc, PWM_V2_CTRL) & PWM_V2_CTRL_ENABLE)
150 	struct rkpwm_softc *sc = cookie;
157 	HCLR4(sc, PWM_V2_CTRL, PWM_V2_CTRL_ENABLE | PWM_V2_CTRL_CONTINUOUS);
162 	rate = sc->sc_clkin;
168 	HWRITE4(sc, PWM_V2_PERIOD, cycles);
169 	HWRITE4(sc, PWM_V2_DUTY, act_cycles);
171 	HCLR4(sc, PWM_V2_CTRL, PWM_V2_CTRL_INACTIVE_POSITIVE);
172 	HCLR4(sc, PWM_V2_CTRL, PWM_V2_CTRL_DUTY_POSITIVE);
175 		HSET4(sc, PWM_V2_CTRL, PWM_V2_CTRL_INACTIVE_POSITIVE);
177 		HSET4(sc, PWM_V2_CTRL, PWM_V2_CTRL_DUTY_POSITIVE);
179 	HSET4(sc, PWM_V2_CTRL, PWM_V2_CTRL_ENABLE | PWM_V2_CTRL_CONTINUOUS);