Lines Matching refs:iommu
121 struct iommu_softc *iommu;
173 struct iommu_softc *iommu;
218 /* AMD iommu */
387 struct iommu_softc *iommu;
392 iommu = dom->iommu;
394 acpidmar_pci_attach(acpidmar_sc, iommu->segment, dd->sid, 1);
396 if (iommu->dte)
400 ctx = &iommu->ctx[sid_bus(dd->sid)][sid_devfn(dd->sid)];
403 printf(" map: %.4x:%.2x:%.2x.%x iommu:%d did:%.4x\n",
404 iommu->segment,
408 iommu->id,
445 struct iommu_softc *iommu;
447 iommu = dom->iommu;
455 for (lvl = iommu->agaw - VTD_STRIDE_SIZE; lvl>= VTD_LEVEL0;
462 iommu_flush_cache(iommu, pte, sizeof(*pte));
466 iommu_alloc_page(iommu, &paddr);
468 iommu_flush_cache(iommu, pte, sizeof(*pte));
489 pte_lvl(struct iommu_softc *iommu, struct pte_entry *pte, vaddr_t va,
498 iommu_alloc_page(iommu, &paddr);
500 iommu_flush_cache(iommu, &pte[idx], sizeof(pte[idx]));
509 struct iommu_softc *iommu;
512 iommu = dom->iommu;
522 pte = pte_lvl(iommu, pte, va, 30, PTE_NXTLVL(2) | PTE_IR | PTE_IW | PTE_P);
523 pte = pte_lvl(iommu, pte, va, 21, PTE_NXTLVL(1) | PTE_IR | PTE_IW | PTE_P);
531 iommu_flush_cache(iommu, pte, sizeof(*pte));
561 if (iommu_bad(dom->iommu)) {
562 printf("unload map no iommu\n");
600 struct iommu_softc *iommu;
606 iommu = dom->iommu;
607 if (!iommu_enabled(iommu)) {
609 if (iommu_enable_translation(iommu, 1)) {
650 if ((iommu->cap & CAP_CM) || acpidmar_force_cm) {
651 iommu_flush_tlb(iommu, IOTLB_DOMAIN, dom->did);
653 iommu_flush_write_buffer(iommu);
664 snprintf(mmm, sizeof(mmm), "%s iommu:%d did:%.4x%s",
665 dmar_bdf(dd->sid), dom->iommu->id, dom->did,
852 iommu_set_rtaddr(struct iommu_softc *iommu, paddr_t paddr)
856 mtx_enter(&iommu->reg_lock);
857 iommu_write_8(iommu, DMAR_RTADDR_REG, paddr);
858 iommu_write_4(iommu, DMAR_GCMD_REG, iommu->gcmd | GCMD_SRTP);
860 sts = iommu_read_4(iommu, DMAR_GSTS_REG);
864 mtx_leave(&iommu->reg_lock);
910 iommu_alloc_page(struct iommu_softc *iommu, paddr_t *paddr)
926 iommu_issue_qi(struct iommu_softc *iommu, struct qi_entry *qi)
931 idx = iommu->qi_head;
932 pi = &iommu->qi[idx];
933 pw = &iommu->qi[(idx+1) % MAXQ];
934 iommu->qi_head = (idx+2) % MAXQ;
945 iommu_flush_tlb_qi(struct iommu_softc *iommu, int mode, int did)
964 if (iommu->cap & CAP_DRD)
966 if (iommu->cap & CAP_DWD)
968 iommu_issue_qi(iommu, &qi);
973 iommu_flush_ctx_qi(struct iommu_softc *iommu, int mode, int did,
992 iommu_issue_qi(iommu, &qi);
997 iommu_flush_write_buffer(struct iommu_softc *iommu)
1001 if (iommu->dte)
1003 if (!(iommu->cap & CAP_RWBF))
1006 iommu_write_4(iommu, DMAR_GCMD_REG, iommu->gcmd | GCMD_WBF);
1008 sts = iommu_read_4(iommu, DMAR_GSTS_REG);
1019 iommu_flush_cache(struct iommu_softc *iommu, void *addr, size_t size)
1021 if (iommu->dte) {
1025 if (!(iommu->ecap & ECAP_C))
1034 iommu_flush_tlb(struct iommu_softc *iommu, int mode, int did)
1040 if (iommu->dte) {
1041 ivhd_invalidate_domain(iommu, did);
1058 if (iommu->cap & CAP_DRD)
1060 if (iommu->cap & CAP_DWD)
1063 mtx_enter(&iommu->reg_lock);
1065 iommu_write_8(iommu, DMAR_IOTLB_REG(iommu), val);
1068 val = iommu_read_8(iommu, DMAR_IOTLB_REG(iommu));
1071 mtx_leave(&iommu->reg_lock);
1078 iommu_flush_ctx(struct iommu_softc *iommu, int mode, int did, int sid, int fm)
1083 if (iommu->dte)
1099 mtx_enter(&iommu->reg_lock);
1102 iommu_write_8(iommu, DMAR_CCMD_REG, val);
1104 val = iommu_read_8(iommu, DMAR_CCMD_REG);
1107 mtx_leave(&iommu->reg_lock);
1112 iommu_enable_qi(struct iommu_softc *iommu, int enable)
1117 if (!(iommu->ecap & ECAP_QI))
1121 iommu->gcmd |= GCMD_QIE;
1123 mtx_enter(&iommu->reg_lock);
1125 iommu_write_4(iommu, DMAR_GCMD_REG, iommu->gcmd);
1127 sts = iommu_read_4(iommu, DMAR_GSTS_REG);
1130 mtx_leave(&iommu->reg_lock);
1134 iommu->gcmd &= ~GCMD_QIE;
1136 mtx_enter(&iommu->reg_lock);
1138 iommu_write_4(iommu, DMAR_GCMD_REG, iommu->gcmd);
1140 sts = iommu_read_4(iommu, DMAR_GSTS_REG);
1143 mtx_leave(&iommu->reg_lock);
1151 iommu_enable_translation(struct iommu_softc *iommu, int enable)
1157 if (iommu->dte)
1161 DPRINTF(0,"enable iommu %d\n", iommu->id);
1162 iommu_showcfg(iommu, -1);
1164 iommu->gcmd |= GCMD_TE;
1169 mtx_enter(&iommu->reg_lock);
1170 iommu_write_4(iommu, DMAR_GCMD_REG, iommu->gcmd);
1174 sts = iommu_read_4(iommu, DMAR_GSTS_REG);
1177 mtx_leave(&iommu->reg_lock);
1182 printf("error.. unable to initialize iommu %d\n",
1183 iommu->id);
1184 iommu->flags |= IOMMU_FLAGS_BAD;
1187 iommu->gcmd &= ~GCMD_TE;
1188 mtx_enter(&iommu->reg_lock);
1189 iommu_write_4(iommu, DMAR_GCMD_REG, iommu->gcmd);
1190 mtx_leave(&iommu->reg_lock);
1195 iommu_flush_ctx(iommu, CTX_GLOBAL, 0, 0, 0);
1196 iommu_flush_tlb(iommu, IOTLB_GLOBAL, 0);
1198 iommu->gcmd &= ~GCMD_TE;
1200 mtx_enter(&iommu->reg_lock);
1202 iommu_write_4(iommu, DMAR_GCMD_REG, iommu->gcmd);
1204 sts = iommu_read_4(iommu, DMAR_GSTS_REG);
1206 mtx_leave(&iommu->reg_lock);
1216 iommu_init(struct acpidmar_softc *sc, struct iommu_softc *iommu,
1225 if (_bus_space_map(sc->sc_memt, dh->address, len, 0, &iommu->ioh) != 0) {
1229 TAILQ_INIT(&iommu->domains);
1230 iommu->id = ++niommu;
1231 iommu->flags = dh->flags;
1232 iommu->segment = dh->segment;
1233 iommu->iot = sc->sc_memt;
1235 iommu->cap = iommu_read_8(iommu, DMAR_CAP_REG);
1236 iommu->ecap = iommu_read_8(iommu, DMAR_ECAP_REG);
1237 iommu->ndoms = cap_nd(iommu->cap);
1241 iommu->cap & CAP_AFL ? "afl " : "", /* adv fault */
1242 iommu->cap & CAP_RWBF ? "rwbf " : "", /* write-buffer flush */
1243 iommu->cap & CAP_PLMR ? "plmr " : "", /* protected lo region */
1244 iommu->cap & CAP_PHMR ? "phmr " : "", /* protected hi region */
1245 iommu->cap & CAP_CM ? "cm " : "", /* caching mode */
1246 iommu->cap & CAP_ZLR ? "zlr " : "", /* zero-length read */
1247 iommu->cap & CAP_PSI ? "psi " : "", /* page invalidate */
1248 iommu->cap & CAP_DWD ? "dwd " : "", /* write drain */
1249 iommu->cap & CAP_DRD ? "drd " : "", /* read drain */
1250 iommu->cap & CAP_FL1GP ? "Gb " : "", /* 1Gb pages */
1251 iommu->cap & CAP_PI ? "pi " : ""); /* posted interrupts */
1253 iommu->ecap & ECAP_C ? "c " : "", /* coherent */
1254 iommu->ecap & ECAP_QI ? "qi " : "", /* queued invalidate */
1255 iommu->ecap & ECAP_DT ? "dt " : "", /* device iotlb */
1256 iommu->ecap & ECAP_IR ? "ir " : "", /* intr remap */
1257 iommu->ecap & ECAP_EIM ? "eim " : "", /* x2apic */
1258 iommu->ecap & ECAP_PT ? "pt " : "", /* passthrough */
1259 iommu->ecap & ECAP_SC ? "sc " : "", /* snoop control */
1260 iommu->ecap & ECAP_ECS ? "ecs " : "", /* extended context */
1261 iommu->ecap & ECAP_MTS ? "mts " : "", /* memory type */
1262 iommu->ecap & ECAP_NEST ? "nest " : "", /* nested translations */
1263 iommu->ecap & ECAP_DIS ? "dis " : "", /* deferred invalidation */
1264 iommu->ecap & ECAP_PASID ? "pas " : "", /* pasid */
1265 iommu->ecap & ECAP_PRS ? "prs " : "", /* page request */
1266 iommu->ecap & ECAP_ERS ? "ers " : "", /* execute request */
1267 iommu->ecap & ECAP_SRS ? "srs " : "", /* supervisor request */
1268 iommu->ecap & ECAP_NWFS ? "nwfs " : "", /* no write flag */
1269 iommu->ecap & ECAP_EAFS ? "eafs " : ""); /* extended accessed flag */
1271 mtx_init(&iommu->reg_lock, IPL_HIGH);
1274 iommu_write_4(iommu, DMAR_FSTS_REG, FSTS_PFO | FSTS_PPF);
1276 iommu->intr = acpidmar_intr_establish(iommu, IPL_HIGH,
1277 acpidmar_intr, iommu, "dmarintr");
1280 sts = iommu_read_4(iommu, DMAR_FECTL_REG);
1281 iommu_write_4(iommu, DMAR_FECTL_REG, sts & ~FECTL_IM);
1284 iommu->root = iommu_alloc_page(iommu, &paddr);
1286 (uint64_t)paddr, iommu->root);
1287 iommu->rtaddr = paddr;
1288 iommu_flush_write_buffer(iommu);
1289 iommu_set_rtaddr(iommu, paddr);
1292 if (iommu->ecap & ECAP_QI) {
1294 iommu->qi = iommu_alloc_page(iommu, &iommu->qip);
1295 iommu_write_8(iommu, DMAR_IQT_REG, 0);
1296 iommu_write_8(iommu, DMAR_IQA_REG, iommu->qip | IQA_QS_256);
1298 if (iommu->ecap & ECAP_IR) {
1300 iommu_write_8(iommu, DMAR_IRTA_REG, 0);
1306 iommu->mgaw = cap_mgaw(iommu->cap);
1307 DPRINTF(0, "gaw: %d { ", iommu->mgaw);
1309 if (cap_sagaw(iommu->cap) & (1L << i)) {
1312 iommu->agaw = gaw;
1318 sts = iommu_read_4(iommu, DMAR_GSTS_REG);
1320 iommu->gcmd |= GCMD_TE;
1322 iommu->gcmd |= GCMD_QIE;
1324 iommu->gcmd |= GCMD_IRE;
1325 DPRINTF(0, "gcmd: %x preset\n", iommu->gcmd);
1326 acpidmar_intr(iommu);
1332 iommu_read_4(struct iommu_softc *iommu, int reg)
1336 v = bus_space_read_4(iommu->iot, iommu->ioh, reg);
1342 iommu_write_4(struct iommu_softc *iommu, int reg, uint32_t v)
1344 bus_space_write_4(iommu->iot, iommu->ioh, reg, (uint32_t)v);
1348 iommu_read_8(struct iommu_softc *iommu, int reg)
1352 v = bus_space_read_8(iommu->iot, iommu->ioh, reg);
1357 iommu_write_8(struct iommu_softc *iommu, int reg, uint64_t v)
1359 bus_space_write_8(iommu->iot, iommu->ioh, reg, v);
1408 domain_create(struct iommu_softc *iommu, int did)
1413 DPRINTF(0, "iommu%d: create domain: %.4x\n", iommu->id, did);
1416 dom->iommu = iommu;
1417 dom->pte = iommu_alloc_page(iommu, &dom->ptep);
1437 iommu->id, dom->did);
1440 gaw = min(iommu->agaw, iommu->mgaw);
1452 TAILQ_INSERT_TAIL(&iommu->domains, dom, link);
1462 DPRINTF(0, "add %s to iommu%d.%.4x\n", dmar_bdf(sid), dom->iommu->id, dom->did);
1487 struct iommu_softc *iommu;
1497 TAILQ_FOREACH(iommu, &sc->sc_drhds, link) {
1498 if (iommu->segment != segment)
1500 /* Check for devscope match or catchall iommu */
1501 rc = acpidmar_match_devscope(&iommu->devices, sc->sc_pc, sid);
1502 if (rc != 0 || iommu->flags) {
1506 if (!iommu) {
1507 printf("%s: no iommu found\n", dmar_bdf(sid));
1512 TAILQ_FOREACH(dom, &iommu->domains, link) {
1520 if (iommu->ndoms <= 2) {
1522 if (!iommu->unity) {
1523 iommu->unity = domain_create(iommu, 1);
1525 dom = iommu->unity;
1527 dom = domain_create(iommu, --iommu->ndoms);
1579 struct iommu_softc *iommu;
1585 iommu = dom->iommu;
1590 if (iommu->dte) {
1591 struct ivhd_dte *dte = &iommu->dte[sid];
1600 ivhd_flush_devtab(iommu, dom->did);
1602 //ivhd_showreg(iommu);
1603 ivhd_showdte(iommu);
1610 if (!root_entry_is_valid(&iommu->root[bus])) {
1611 iommu->ctx[bus] = iommu_alloc_page(iommu, &paddr);
1612 iommu->root[bus].lo = paddr | ROOT_P;
1613 iommu_flush_cache(iommu, &iommu->root[bus],
1615 DPRINTF(0, "iommu%d: Allocate context for bus: %.2x pa:%.16llx va:%p\n",
1616 iommu->id, bus, (uint64_t)paddr,
1617 iommu->ctx[bus]);
1621 ctx = iommu->ctx[bus] + devfn;
1624 lvl = VTD_AWTOLEVEL(iommu->agaw);
1634 iommu_flush_cache(iommu, ctx, sizeof(struct context_entry));
1635 if ((iommu->cap & CAP_CM) || acpidmar_force_cm) {
1636 iommu_flush_ctx(iommu, CTX_DEVICE, dom->did, sid, 0);
1637 iommu_flush_tlb(iommu, IOTLB_GLOBAL, 0);
1639 iommu_flush_write_buffer(iommu);
1641 DPRINTF(0, "iommu%d: %s set context ptep:%.16llx lvl:%d did:%.4x tt:%d\n",
1642 iommu->id, dmar_bdf(sid), (uint64_t)dom->ptep, lvl,
1752 struct iommu_softc *iommu;
1758 iommu = malloc(sizeof(*iommu), M_DEVBUF, M_ZERO | M_WAITOK);
1760 &iommu->devices);
1761 iommu_init(sc, iommu, &de->drhd);
1765 TAILQ_INSERT_TAIL(&sc->sc_drhds, iommu, link);
1767 TAILQ_INSERT_HEAD(&sc->sc_drhds, iommu, link);
1839 struct iommu_softc *iommu;
1877 /* Pre-create domains for iommu devices */
1878 TAILQ_FOREACH(iommu, &sc->sc_drhds, link) {
1879 TAILQ_FOREACH(dl, &iommu->devices, link) {
1882 dom = acpidmar_pci_attach(sc, iommu->segment, sid, 0);
1884 printf("%.4x:%.2x:%.2x.%x iommu:%d did:%.4x\n",
1885 iommu->segment, dl->bus, dl->dp[0].device, dl->dp[0].function,
1886 iommu->id, dom->did);
1920 void ivhd_checkerr(struct iommu_softc *iommu);
1926 struct iommu_softc *iommu = ctx;
1928 if (!iommu->dte)
1930 ivhd_poll_events(iommu);
1936 ivhd_intr_map(struct iommu_softc *iommu, int devid) {
1939 if (iommu->intr)
1944 iommu->intr = pci_intr_establish(NULL, ih, IPL_NET | IPL_MPSAFE,
1945 acpiivhd_intr, iommu, "amd_iommu");
1946 printf("amd iommu intr: %p\n", iommu->intr);
1973 ivhd_showpage(struct iommu_softc *iommu, int sid, paddr_t paddr)
1985 iommu->dte[sid].dw0,
1986 iommu->dte[sid].dw1,
1987 iommu->dte[sid].dw2,
1988 iommu->dte[sid].dw3,
1989 iommu->dte[sid].dw4,
1990 iommu->dte[sid].dw5,
1991 iommu->dte[sid].dw6,
1992 iommu->dte[sid].dw7);
1998 ivhd_show_event(struct iommu_softc *iommu, struct ivhd_event *evt, int head)
2019 ivhd_showdte(iommu);
2030 ivhd_showdte(iommu);
2031 ivhd_showpage(iommu, sid, address);
2039 ivhd_showdte(iommu);
2047 ivhd_showdte(iommu);
2051 ivhd_showcmd(iommu);
2056 ivhd_showcmd(iommu);
2079 ivhd_poll_events(struct iommu_softc *iommu)
2085 head = iommu_read_4(iommu, EVT_HEAD_REG);
2086 tail = iommu_read_4(iommu, EVT_TAIL_REG);
2092 ivhd_show_event(iommu, iommu->evt_tbl + head, head);
2095 iommu_write_4(iommu, EVT_HEAD_REG, head);
2101 _ivhd_issue_command(struct iommu_softc *iommu, const struct ivhd_command *cmd)
2107 head = iommu_read_4(iommu, CMD_HEAD_REG);
2110 tail = iommu_read_4(iommu, CMD_TAIL_REG);
2118 memcpy(iommu->cmd_tbl + tail, cmd, sz);
2119 iommu_write_4(iommu, CMD_TAIL_REG, next);
2127 ivhd_issue_command(struct iommu_softc *iommu, const struct ivhd_command *cmd, int wait)
2134 rc = _ivhd_issue_command(iommu, cmd);
2144 rc = _ivhd_issue_command(iommu, &wq);
2160 ivhd_flush_devtab(struct iommu_softc *iommu, int did)
2167 return ivhd_issue_command(iommu, &cmd, 1);
2172 ivhd_invalidate_iommu_all(struct iommu_softc *iommu)
2178 return ivhd_issue_command(iommu, &cmd, 0);
2183 ivhd_invalidate_interrupt_table(struct iommu_softc *iommu, int did)
2190 return ivhd_issue_command(iommu, &cmd, 0);
2195 ivhd_invalidate_domain(struct iommu_softc *iommu, int did)
2201 return ivhd_issue_command(iommu, &cmd, 1);
2206 ivhd_showreg(struct iommu_softc *iommu)
2209 iommu_read_8(iommu, DEV_TAB_BASE_REG),
2210 iommu_read_8(iommu, CMD_BASE_REG),
2211 iommu_read_8(iommu, EVT_BASE_REG),
2212 iommu_read_8(iommu, IOMMUCTL_REG),
2213 iommu_read_8(iommu, IOMMUSTS_REG));
2215 iommu_read_8(iommu, CMD_HEAD_REG),
2216 iommu_read_8(iommu, CMD_TAIL_REG),
2217 iommu_read_8(iommu, EVT_HEAD_REG),
2218 iommu_read_8(iommu, EVT_TAIL_REG));
2223 ivhd_checkerr(struct iommu_softc *iommu)
2228 iommu->dte[0x2303].dw0 = -1; /* invalid */
2229 iommu->dte[0x2303].dw2 = 0x1234; /* domain */
2230 iommu->dte[0x2303].dw7 = -1; /* reserved */
2231 ivhd_flush_devtab(iommu, 0x1234);
2232 ivhd_poll_events(iommu);
2235 ivhd_issue_command(iommu, &cmd, 0);
2236 ivhd_poll_events(iommu);
2243 ivhd_showdte(struct iommu_softc *iommu)
2248 if (iommu->dte[i].dw0) {
2251 iommu->dte[i].dw0, iommu->dte[i].dw1,
2252 iommu->dte[i].dw2, iommu->dte[i].dw3,
2253 iommu->dte[i].dw4, iommu->dte[i].dw5,
2254 iommu->dte[i].dw6, iommu->dte[i].dw7);
2261 ivhd_showcmd(struct iommu_softc *iommu)
2267 ihd = iommu->cmd_tbl;
2268 phd = iommu_read_8(iommu, CMD_BASE_REG) & CMD_BASE_MASK;
2276 #define _c(x) (int)((iommu->ecap >> x ##_SHIFT) & x ## _MASK)
2280 ivhd_iommu_init(struct acpidmar_softc *sc, struct iommu_softc *iommu,
2287 if (sc == NULL || iommu == NULL || ivhd == NULL) {
2291 if (_bus_space_map(sc->sc_memt, ivhd->address, 0x80000, 0, &iommu->ioh) != 0) {
2295 TAILQ_INIT(&iommu->domains);
2296 TAILQ_INIT(&iommu->devices);
2299 iommu->id = ++niommu;
2300 iommu->iot = sc->sc_memt;
2301 iommu->mgaw = 48;
2302 iommu->agaw = 48;
2303 iommu->flags = 1;
2304 iommu->segment = 0;
2305 iommu->ndoms = 256;
2307 printf(": AMD iommu%d at 0x%.8llx\n", iommu->id, ivhd->address);
2309 iommu->ecap = iommu_read_8(iommu, EXTFEAT_REG);
2310 DPRINTF(0,"iommu%d: ecap:%.16llx ", iommu->id, iommu->ecap);
2312 iommu->ecap & EFR_PREFSUP ? "pref " : "",
2313 iommu->ecap & EFR_PPRSUP ? "ppr " : "",
2314 iommu->ecap & EFR_NXSUP ? "nx " : "",
2315 iommu->ecap & EFR_GTSUP ? "gt " : "",
2316 iommu->ecap & EFR_IASUP ? "ia " : "",
2317 iommu->ecap & EFR_GASUP ? "ga " : "",
2318 iommu->ecap & EFR_HESUP ? "he " : "",
2319 iommu->ecap & EFR_PCSUP ? "pc " : "");
2324 /* Turn off iommu */
2325 ov = iommu_read_8(iommu, IOMMUCTL_REG);
2326 iommu_write_8(iommu, IOMMUCTL_REG, ov & ~(CTL_IOMMUEN | CTL_COHERENT |
2331 ivhd_intr_map(iommu, ivhd->devid);
2334 iommu->cmd_tbl = iommu_alloc_page(iommu, &paddr);
2335 iommu_write_8(iommu, CMD_BASE_REG, (paddr & CMD_BASE_MASK) | CMD_TBL_LEN_4K);
2336 iommu_write_4(iommu, CMD_HEAD_REG, 0x00);
2337 iommu_write_4(iommu, CMD_TAIL_REG, 0x00);
2338 iommu->cmd_tblp = paddr;
2341 iommu->evt_tbl = iommu_alloc_page(iommu, &paddr);
2342 iommu_write_8(iommu, EVT_BASE_REG, (paddr & EVT_BASE_MASK) | EVT_TBL_LEN_4K);
2343 iommu_write_4(iommu, EVT_HEAD_REG, 0x00);
2344 iommu_write_4(iommu, EVT_TAIL_REG, 0x00);
2345 iommu->evt_tblp = paddr;
2350 iommu->dte = sc->sc_hwdte;
2351 iommu_write_8(iommu, DEV_TAB_BASE_REG, (sc->sc_hwdtep & DEV_TAB_MASK) | DEV_TAB_LEN);
2367 iommu_write_8(iommu, IOMMUCTL_REG, ov);
2369 ivhd_invalidate_iommu_all(iommu);
2371 TAILQ_INSERT_TAIL(&sc->sc_drhds, iommu, link);
2378 struct iommu_softc *iommu;
2409 iommu = malloc(sizeof(*iommu), M_DEVBUF, M_ZERO|M_WAITOK);
2410 ivhd_iommu_init(sc, iommu, ivhd);
2543 acpiivhd_activate(struct iommu_softc *iommu, int act)
2547 iommu->flags |= IOMMU_FLAGS_SUSPEND;
2550 iommu->flags &= ~IOMMU_FLAGS_SUSPEND;
2560 struct iommu_softc *iommu;
2570 TAILQ_FOREACH(iommu, &sc->sc_drhds, link) {
2571 printf("iommu%d resume\n", iommu->id);
2572 if (iommu->dte) {
2573 acpiivhd_activate(iommu, act);
2576 iommu_flush_write_buffer(iommu);
2577 iommu_set_rtaddr(iommu, iommu->rtaddr);
2578 iommu_write_4(iommu, DMAR_FEDATA_REG, iommu->fedata);
2579 iommu_write_4(iommu, DMAR_FEADDR_REG, iommu->feaddr);
2580 iommu_write_4(iommu, DMAR_FEUADDR_REG,
2581 iommu->feaddr >> 32);
2582 if ((iommu->flags & (IOMMU_FLAGS_BAD|IOMMU_FLAGS_SUSPEND)) ==
2585 iommu_enable_translation(iommu, 1);
2587 iommu_showcfg(iommu, -1);
2591 TAILQ_FOREACH(iommu, &sc->sc_drhds, link) {
2592 printf("iommu%d suspend\n", iommu->id);
2593 if (iommu->flags & IOMMU_FLAGS_BAD)
2595 if (iommu->dte) {
2596 acpiivhd_activate(iommu, act);
2599 iommu->flags |= IOMMU_FLAGS_SUSPEND;
2600 iommu_enable_translation(iommu, 0);
2601 iommu_showcfg(iommu, -1);
2660 struct iommu_softc *iommu = ip->iommu;
2664 mtx_enter(&iommu->reg_lock);
2666 iommu_write_4(iommu, DMAR_FECTL_REG, FECTL_IM);
2667 iommu_read_4(iommu, DMAR_FECTL_REG);
2669 mtx_leave(&iommu->reg_lock);
2676 struct iommu_softc *iommu = ip->iommu;
2680 mtx_enter(&iommu->reg_lock);
2682 iommu_write_4(iommu, DMAR_FECTL_REG, 0);
2683 iommu_read_4(iommu, DMAR_FECTL_REG);
2685 mtx_leave(&iommu->reg_lock);
2693 struct iommu_softc *iommu = ip->iommu;
2695 mtx_enter(&iommu->reg_lock);
2697 iommu->fedata = vec;
2698 iommu->feaddr = 0xfee00000L | (ci->ci_apicid << 12);
2699 iommu_write_4(iommu, DMAR_FEDATA_REG, vec);
2700 iommu_write_4(iommu, DMAR_FEADDR_REG, iommu->feaddr);
2701 iommu_write_4(iommu, DMAR_FEUADDR_REG, iommu->feaddr >> 32);
2703 mtx_leave(&iommu->reg_lock);
2717 struct iommu_softc *iommu = ctx;
2720 pic = &iommu->pic.pic;
2721 iommu->pic.iommu = iommu;
2742 struct iommu_softc *iommu = ctx;
2750 if (!(iommu->gcmd & GCMD_TE)) {
2753 mtx_enter(&iommu->reg_lock);
2754 sts = iommu_read_4(iommu, DMAR_FECTL_REG);
2755 sts = iommu_read_4(iommu, DMAR_FSTS_REG);
2758 mtx_leave(&iommu->reg_lock);
2762 nfr = cap_nfr(iommu->cap);
2763 fro = cap_fro(iommu->cap);
2766 fe.hi = iommu_read_8(iommu, fro + (fri*16) + 8);
2770 fe.lo = iommu_read_8(iommu, fro + (fri*16));
2772 iommu_showfault(iommu, fri, &fe);
2779 iommu_write_4(iommu, DMAR_FSTS_REG, FSTS_PFO | FSTS_PPF);
2781 mtx_leave(&iommu->reg_lock);
2835 iommu_showcfg(struct iommu_softc *iommu, int sid)
2842 cmd = iommu_read_4(iommu, DMAR_GCMD_REG);
2843 sts = iommu_read_4(iommu, DMAR_GSTS_REG);
2844 printf("iommu%d: flags:%d root pa:%.16llx %s %s %s %.8x %.8x\n",
2845 iommu->id, iommu->flags, iommu_read_8(iommu, DMAR_RTADDR_REG),
2851 if (!root_entry_is_valid(&iommu->root[i])) {
2855 ctx = iommu->ctx[i] + j;
2871 iommu_showpte(ctx->lo & ~VTD_PAGE_MASK, iommu->agaw -
2880 iommu_showfault(struct iommu_softc *iommu, int fri, struct fault_entry *fe)
2894 iommu_showcfg(iommu, mksid(bus,dev,fun));
2895 if (!iommu->ctx[bus]) {
2898 } else if (!context_entry_is_valid(&iommu->ctx[bus][df])) {
2901 } else if (context_user(&iommu->ctx[bus][df]) != 0xA) {
2908 printf("fri%d: dmar: %.2x:%.2x.%x %s error at %llx fr:%d [%s] iommu:%d [%s]\n",
2913 iommu->id,