Lines Matching refs:SET
83 SET(reg_flags, PKO_REG_FLAGS_ENA_DWB);
84 SET(reg_flags, PKO_REG_FLAGS_ENA_PKO);
99 SET(reg_flags, PKO_REG_FLAGS_RESET);
109 SET(reg_cmd_buf, (sc->sc_cmd_buf_pool << 20) & PKO_REG_CMD_BUF_POOL);
110 SET(reg_cmd_buf, sc->sc_cmd_buf_size & PKO_REG_CMD_BUF_SIZE);
121 SET(reg_read_idx, sc->sc_port & PKO_REG_READ_IDX_IDX);
126 SET(mem_queue_qos, ((uint64_t)sc->sc_port << 7) & PKO_MEM_QUEUE_QOS_PID);
127 SET(mem_queue_qos, sc->sc_port & PKO_MEM_QUEUE_QOS_QID);
128 SET(mem_queue_qos, ((enable ? 0xffULL : 0x00ULL) << 53) &
161 SET(val, 10ULL << PKO_MEM_PORT_PTRS_EID_S);
163 SET(val, 40ULL << PKO_MEM_PORT_PTRS_BP_PORT_S);
172 SET(mem_queue_ptrs, PKO_MEM_QUEUE_PTRS_TAIL);
173 SET(mem_queue_ptrs, ((uint64_t)0 << 13) & PKO_MEM_QUEUE_PTRS_IDX);
174 SET(mem_queue_ptrs, ((uint64_t)sc->sc_port << 7) & PKO_MEM_QUEUE_PTRS_PID);
175 SET(mem_queue_ptrs, sc->sc_port & PKO_MEM_QUEUE_PTRS_QID);
176 SET(mem_queue_ptrs, ((uint64_t)0xff << 53) & PKO_MEM_QUEUE_PTRS_QOS_MASK);
177 SET(mem_queue_ptrs, ((uint64_t)buf_ptr << 17) & PKO_MEM_QUEUE_PTRS_BUF_PTR);