octeon/dev/cn30xxgmx.c

463 			SET(prt_cfg, PRTN_CFG_EN);
511 		SET(ovr_bp, (1 << index) << TX_OVR_BP_BP_SHIFT);
513 		SET(ovr_bp, (1 << index) << TX_OVR_BP_IGN_FULL_SHIFT);
515 		SET(ovr_bp, (1 << index) << TX_OVR_BP_EN_SHIFT);
518 		SET(ovr_bp, (1 << index) << TX_OVR_BP_IGN_FULL_SHIFT);
541 	SET(tx_int_xxx,
556 	SET(rx_int_xxx, 0 |
609 		SET(tmp, rx_frm_ctl);
640 	SET(ctl, RXN_ADR_CTL_BCST);
643 		SET(ifp->if_flags, IFF_ALLMULTI);
644 		SET(ctl, RXN_ADR_CTL_MCST_ACCEPT);
646 		SET(ifp->if_flags, IFF_ALLMULTI);
647 		SET(ctl, RXN_ADR_CTL_CAM_MODE);
648 		SET(ctl, RXN_ADR_CTL_MCST_ACCEPT);
651 		SET(ctl, RXN_ADR_CTL_CAM_MODE);
652 		SET(ctl, RXN_ADR_CTL_MCST_AFCAM);
797 	SET(val, AGL_PRT_CTL_COMP);
823 	SET(val, AGL_GMX_PRT_CFG_RX_EN);
824 	SET(val, AGL_GMX_PRT_CFG_TX_EN);
828 	SET(val, AGL_GMX_PRT_CFG_EN);
883 		SET(prt_cfg, AGL_GMX_PRT_CFG_DUPLEX);
890 		SET(prt_cfg, AGL_GMX_PRT_CFG_SPEED_MSB);
892 		SET(prt_cfg, AGL_GMX_PRT_CFG_BURST);
899 		SET(prt_cfg, AGL_GMX_PRT_CFG_BURST);
904 		SET(prt_cfg, AGL_GMX_PRT_CFG_SPEED);
906 		SET(prt_cfg, AGL_GMX_PRT_CFG_SLOTTIME);
908 			SET(prt_cfg, AGL_GMX_PRT_CFG_BURST);
920 	SET(val, clk_cnt << AGL_GMX_TX_CLK_CLK_CNT_S);
933 	SET(val, AGL_PRT_CTL_CLKRST);
937 	SET(val, AGL_PRT_CTL_ENABLE);
1196 		SET(prt_cfg, PRTN_CFG_SLOTTIME);
1202 		SET(prt_cfg, PRTN_CFG_SPEED);
1211 		SET(prt_cfg, PRTN_CFG_SLOTTIME);
1212 		SET(prt_cfg, PRTN_CFG_SPEED);
1223 		SET(prt_cfg, PRTN_CFG_DUPLEX);
1321 	SET(timer_count, ((1600 * cpu_freq) >> 10) & PCS_LINK_TIMER_COUNT_MASK);
1326 	SET(ctl_reg, PCS_MR_CONTROL_RESET);
1344 	SET(ctl_reg, PCS_MR_CONTROL_AN_EN);
1345 	SET(ctl_reg, PCS_MR_CONTROL_RST_AN);
1378 		SET(prt_cfg, PRTN_CFG_DUPLEX);
1389 		SET(misc_ctl, PCS_MISC_CTL_GMXENO);
1396 		SET(prt_cfg, PRTN_CFG_SPEED_MSB);
1412 		SET(prt_cfg, PRTN_CFG_SPEED);
1414 		SET(prt_cfg, PRTN_CFG_SLOTTIME);