Lines Matching refs:sc
219 cpsw_set_txdesc_next(struct cpsw_softc * const sc, const u_int i, uint32_t n)
222 bus_space_write_4(sc->sc_bst, sc->sc_bsh_txdescs, o, n);
226 cpsw_set_rxdesc_next(struct cpsw_softc * const sc, const u_int i, uint32_t n)
229 bus_space_write_4(sc->sc_bst, sc->sc_bsh_rxdescs, o, n);
233 cpsw_get_txdesc(struct cpsw_softc * const sc, const u_int i,
237 bus_space_read_region_4(sc->sc_bst, sc->sc_bsh_txdescs, o,
242 cpsw_set_txdesc(struct cpsw_softc * const sc, const u_int i,
246 bus_space_write_region_4(sc->sc_bst, sc->sc_bsh_txdescs, o,
251 cpsw_get_rxdesc(struct cpsw_softc * const sc, const u_int i,
255 bus_space_read_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, o,
260 cpsw_set_rxdesc(struct cpsw_softc * const sc, const u_int i,
264 bus_space_write_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, o,
269 cpsw_txdesc_paddr(struct cpsw_softc * const sc, u_int x)
272 return sc->sc_txdescs_pa + sizeof(struct cpsw_cpdma_bd) * x;
276 cpsw_rxdesc_paddr(struct cpsw_softc * const sc, u_int x)
279 return sc->sc_rxdescs_pa + sizeof(struct cpsw_cpdma_bd) * x;
283 cpsw_mdio_init(struct cpsw_softc *sc)
288 sc->sc_active_port = 0;
292 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MDIOCONTROL,
296 alive = bus_space_read_4(sc->sc_bst, sc->sc_bsh, MDIOALIVE) & 3;
303 printf("%s: no PHY is alive\n", DEVNAME(sc));
307 link = bus_space_read_4(sc->sc_bst, sc->sc_bsh, MDIOLINK) & 3;
312 sc->sc_active_port = 1;
314 sc->sc_active_port = 1;
317 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MDIOUSERPHYSEL0,
318 sc->sc_active_port);
332 struct cpsw_softc *sc = (struct cpsw_softc *)self;
334 struct arpcom * const ac = &sc->sc_ac;
362 timeout_set(&sc->sc_tick, cpsw_tick, sc);
364 cpsw_get_port_config(sc->sc_port_config, faa->fa_node);
365 memcpy(sc->sc_ac.ac_enaddr, sc->sc_port_config[0].enaddr,
368 sc->sc_rxthih = arm_intr_establish_fdt_idx(faa->fa_node, 0, IPL_NET,
369 cpsw_rxthintr, sc, DEVNAME(sc));
370 sc->sc_rxih = arm_intr_establish_fdt_idx(faa->fa_node, 1, IPL_NET,
371 cpsw_rxintr, sc, DEVNAME(sc));
372 sc->sc_txih = arm_intr_establish_fdt_idx(faa->fa_node, 2, IPL_NET,
373 cpsw_txintr, sc, DEVNAME(sc));
374 sc->sc_miscih = arm_intr_establish_fdt_idx(faa->fa_node, 3, IPL_NET,
375 cpsw_miscintr, sc, DEVNAME(sc));
377 sc->sc_bst = faa->fa_iot;
378 sc->sc_bdt = faa->fa_dmat;
380 error = bus_space_map(sc->sc_bst, faa->fa_reg[0].addr,
381 memsize, BUS_SPACE_MAP_LINEAR, &sc->sc_bsh);
387 error = bus_space_subregion(sc->sc_bst, sc->sc_bsh,
389 &sc->sc_bsh_txdescs);
394 descs = bus_space_vaddr(sc->sc_bst, sc->sc_bsh_txdescs);
395 pmap_extract(pmap_kernel(), (vaddr_t)descs, &sc->sc_txdescs_pa);
397 error = bus_space_subregion(sc->sc_bst, sc->sc_bsh,
399 &sc->sc_bsh_rxdescs);
404 descs = bus_space_vaddr(sc->sc_bst, sc->sc_bsh_rxdescs);
405 pmap_extract(pmap_kernel(), (vaddr_t)descs, &sc->sc_rxdescs_pa);
407 sc->sc_rdp = malloc(sizeof(*sc->sc_rdp), M_TEMP, M_WAITOK);
408 KASSERT(sc->sc_rdp != NULL);
411 if ((error = bus_dmamap_create(sc->sc_bdt, MCLBYTES,
413 &sc->sc_rdp->tx_dm[i])) != 0) {
416 sc->sc_rdp->tx_mb[i] = NULL;
420 if ((error = bus_dmamap_create(sc->sc_bdt, MCLBYTES, 1,
421 MCLBYTES, 0, 0, &sc->sc_rdp->rx_dm[i])) != 0) {
424 sc->sc_rdp->rx_mb[i] = NULL;
427 sc->sc_txpad = dma_alloc(ETHER_MIN_LEN, PR_WAITOK | PR_ZERO);
428 KASSERT(sc->sc_txpad != NULL);
429 bus_dmamap_create(sc->sc_bdt, ETHER_MIN_LEN, 1, ETHER_MIN_LEN, 0,
430 BUS_DMA_WAITOK, &sc->sc_txpad_dm);
431 bus_dmamap_load(sc->sc_bdt, sc->sc_txpad_dm, sc->sc_txpad,
433 bus_dmamap_sync(sc->sc_bdt, sc->sc_txpad_dm, 0, ETHER_MIN_LEN,
436 idver = bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_SS_IDVER);
441 ifp->if_softc = sc;
448 memcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ);
452 sc->sc_mii.mii_ifp = ifp;
453 sc->sc_mii.mii_readreg = cpsw_mii_readreg;
454 sc->sc_mii.mii_writereg = cpsw_mii_writereg;
455 sc->sc_mii.mii_statchg = cpsw_mii_statchg;
457 cpsw_mdio_init(sc);
459 ifmedia_init(&sc->sc_mii.mii_media, 0, cpsw_mediachange,
461 mii_attach(self, &sc->sc_mii, 0xffffffff,
462 sc->sc_port_config[0].phy_id, MII_OFFSET_ANY, 0);
463 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
465 ifmedia_add(&sc->sc_mii.mii_media,
467 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL);
469 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
481 struct cpsw_softc *sc = ifp->if_softc;
483 if (LIST_FIRST(&sc->sc_mii.mii_phys))
484 mii_mediachg(&sc->sc_mii);
492 struct cpsw_softc *sc = ifp->if_softc;
494 if (LIST_FIRST(&sc->sc_mii.mii_phys)) {
495 mii_pollstat(&sc->sc_mii);
496 ifmr->ifm_active = sc->sc_mii.mii_media_active;
497 ifmr->ifm_status = sc->sc_mii.mii_media_status;
504 struct cpsw_softc * const sc = ifp->if_softc;
505 struct cpsw_ring_data * const rdp = sc->sc_rdp;
522 if (sc->sc_txnext >= sc->sc_txhead)
523 txfree = CPSW_NTXDESCS - 1 + sc->sc_txhead - sc->sc_txnext;
525 txfree = sc->sc_txhead - sc->sc_txnext - 1;
537 dm = rdp->tx_dm[sc->sc_txnext];
538 error = bus_dmamap_load_mbuf(sc->sc_bdt, dm, m, BUS_DMA_NOWAIT);
545 bus_dmamap_load_mbuf(sc->sc_bdt, dm, m,
559 KASSERT(rdp->tx_mb[sc->sc_txnext] == NULL);
560 rdp->tx_mb[sc->sc_txnext] = m;
567 bus_dmamap_sync(sc->sc_bdt, dm, 0, dm->dm_mapsize,
571 txstart = sc->sc_txnext;
572 eopi = sc->sc_txnext;
574 bd.next = cpsw_txdesc_paddr(sc,
575 TXDESC_NEXT(sc->sc_txnext));
590 cpsw_set_txdesc(sc, sc->sc_txnext, &bd);
592 eopi = sc->sc_txnext;
593 sc->sc_txnext = TXDESC_NEXT(sc->sc_txnext);
596 bd.next = cpsw_txdesc_paddr(sc,
597 TXDESC_NEXT(sc->sc_txnext));
598 bd.bufptr = sc->sc_txpad_pa;
604 cpsw_set_txdesc(sc, sc->sc_txnext, &bd);
606 eopi = sc->sc_txnext;
607 sc->sc_txnext = TXDESC_NEXT(sc->sc_txnext);
614 KASSERT(eopi == TXDESC_PREV(sc->sc_txnext));
615 cpsw_set_txdesc_next(sc, TXDESC_PREV(sc->sc_txnext), 0);
618 cpsw_set_txdesc_next(sc, TXDESC_PREV(txstart),
619 cpsw_txdesc_paddr(sc, txstart));
620 if (sc->sc_txeoq) {
622 sc->sc_txeoq = false;
623 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_HDP(0),
624 cpsw_txdesc_paddr(sc, txstart));
632 struct cpsw_softc *sc = ifp->if_softc;
656 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
659 error = ether_ioctl(ifp, &sc->sc_ac, cmd, data);
684 cpsw_mii_wait(struct cpsw_softc * const sc, int reg)
689 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg) & (1U << 31)) == 0)
699 struct cpsw_softc * const sc = (struct cpsw_softc *)dev;
702 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0)
705 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MDIOUSERACCESS0, (1U << 31) |
708 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0)
711 v = bus_space_read_4(sc->sc_bst, sc->sc_bsh, MDIOUSERACCESS0);
721 struct cpsw_softc * const sc = (struct cpsw_softc *)dev;
726 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0)
729 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MDIOUSERACCESS0, (1U << 31) | (1 << 30) |
732 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0)
735 v = bus_space_read_4(sc->sc_bst, sc->sc_bsh, MDIOUSERACCESS0);
749 cpsw_new_rxbuf(struct cpsw_softc * const sc, const u_int i)
751 struct cpsw_ring_data * const rdp = sc->sc_rdp;
771 bus_dmamap_unload(sc->sc_bdt, rdp->rx_dm[i]);
777 error = bus_dmamap_load_mbuf(sc->sc_bdt, rdp->rx_dm[i], rdp->rx_mb[i],
783 bus_dmamap_sync(sc->sc_bdt, rdp->rx_dm[i],
797 cpsw_set_rxdesc(sc, i, &bd);
799 cpsw_set_rxdesc_next(sc, h, cpsw_rxdesc_paddr(sc, i));
807 struct cpsw_softc * const sc = ifp->if_softc;
808 struct arpcom *ac = &sc->sc_ac;
809 struct mii_data * const mii = &sc->sc_mii;
814 sc->sc_txnext = 0;
815 sc->sc_txhead = 0;
818 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_WR_SOFT_RESET, 1);
819 while(bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_WR_SOFT_RESET) & 1);
822 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_SS_SOFT_RESET, 1);
823 while(bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_SS_SOFT_RESET) & 1);
826 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_ALE_CONTROL, (3 << 30) | 0x10);
831 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_SL_SOFT_RESET(i), 1);
832 while(bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_SL_SOFT_RESET(i)) & 1);
834 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_SL_RX_PRI_MAP(i), 0x76543210);
835 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_PORT_P_TX_PRI_MAP(i+1), 0x33221100);
836 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_SL_RX_MAXLEN(i), 0x5f2);
838 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_PORT_P_SA_HI(i+1),
841 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_PORT_P_SA_LO(i+1),
846 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_SL_MACCONTROL(i),
850 if (i == sc->sc_active_port)
851 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_ALE_PORTCTL(i+1), 3);
855 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210);
856 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0);
859 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_ALE_PORTCTL(0), 3);
861 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_SS_PTYPE, 0);
862 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_SS_STAT_PORT_EN, 7);
864 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_SOFT_RESET, 1);
865 while(bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_SOFT_RESET) & 1);
868 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_HDP(i), 0);
869 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_RX_HDP(i), 0);
870 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_CP(i), 0);
871 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_RX_CP(i), 0);
874 bus_space_set_region_4(sc->sc_bst, sc->sc_bsh_txdescs, 0, 0,
877 sc->sc_txhead = 0;
878 sc->sc_txnext = 0;
880 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_RX_FREEBUFFER(0), 0);
882 bus_space_set_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, 0, 0,
886 cpsw_set_rxdesc_next(sc, RXDESC_PREV(0), 0);
888 cpsw_new_rxbuf(sc, i);
890 sc->sc_rxhead = 0;
893 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_RX_BUFFER_OFFSET, ETHER_ALIGN);
896 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF);
897 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF);
900 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_CONTROL, 1);
901 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_RX_CONTROL, 1);
905 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_WR_C_RX_IMAX(0), 2);
906 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_WR_C_TX_IMAX(0), 2);
907 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_WR_INT_CONTROL, 3 << 16 | CPSW_VBUSP_CLK_MHZ/4);
910 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_WR_C_TX_EN(0), 1);
911 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_WR_C_RX_EN(0), 1);
912 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_WR_C_MISC_EN(0), 0x1F);
915 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_DMA_INTMASK_SET, 2);
918 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_INTMASK_SET, 1);
919 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_RX_INTMASK_SET, 1);
922 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RXTH);
923 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RX);
924 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX);
925 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC);
927 cpsw_mdio_init(sc);
932 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_RX_HDP(0), cpsw_rxdesc_paddr(sc, 0));
933 sc->sc_rxrun = true;
934 sc->sc_rxeoq = false;
936 sc->sc_txrun = true;
937 sc->sc_txeoq = true;
942 timeout_add_sec(&sc->sc_tick, 1);
950 struct cpsw_softc * const sc = ifp->if_softc;
951 struct cpsw_ring_data * const rdp = sc->sc_rdp;
961 timeout_del(&sc->sc_tick);
963 mii_down(&sc->sc_mii);
965 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_INTMASK_CLEAR, 1);
966 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_RX_INTMASK_CLEAR, 1);
967 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_WR_C_TX_EN(0), 0x0);
968 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_WR_C_RX_EN(0), 0x0);
969 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_WR_C_MISC_EN(0), 0x1F);
971 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_TEARDOWN, 0);
972 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_RX_TEARDOWN, 0);
974 while ((sc->sc_txrun || sc->sc_rxrun) && i < 10000) {
976 if ((sc->sc_txrun == true) && cpsw_txintr(sc) == 0)
977 sc->sc_txrun = false;
978 if ((sc->sc_rxrun == true) && cpsw_rxintr(sc) == 0)
979 sc->sc_rxrun = false;
985 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_WR_SOFT_RESET, 1);
986 while(bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_WR_SOFT_RESET) & 1);
989 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_SS_SOFT_RESET, 1);
990 while(bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_SS_SOFT_RESET) & 1);
993 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_SL_SOFT_RESET(i), 1);
994 while(bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_SL_SOFT_RESET(i)) & 1);
998 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_SOFT_RESET, 1);
999 while(bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_SOFT_RESET) & 1);
1003 bus_dmamap_unload(sc->sc_bdt, rdp->tx_dm[i]);
1021 bus_dmamap_unload(sc->sc_bdt, rdp->rx_dm[i]);
1030 struct cpsw_softc * const sc = arg;
1033 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RXTH);
1041 struct cpsw_softc * const sc = arg;
1042 struct ifnet * const ifp = &sc->sc_ac.ac_if;
1043 struct cpsw_ring_data * const rdp = sc->sc_rdp;
1051 sc->sc_rxeoq = false;
1054 KASSERT(sc->sc_rxhead < CPSW_NRXDESCS);
1056 i = sc->sc_rxhead;
1063 cpsw_get_rxdesc(sc, i, &bd);
1069 sc->sc_rxrun = false;
1073 bus_dmamap_sync(sc->sc_bdt, dm, 0, dm->dm_mapsize,
1076 if (cpsw_new_rxbuf(sc, i) != 0) {
1104 sc->sc_rxhead = RXDESC_NEXT(sc->sc_rxhead);
1106 sc->sc_rxeoq = true;
1107 sc->sc_rxrun = false;
1109 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_RX_CP(0),
1110 cpsw_rxdesc_paddr(sc, i));
1113 if (sc->sc_rxeoq) {
1114 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_RX_HDP(0),
1115 cpsw_rxdesc_paddr(sc, sc->sc_rxhead));
1116 sc->sc_rxrun = true;
1117 sc->sc_rxeoq = false;
1120 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_CPDMA_EOI_VECTOR,
1132 struct cpsw_softc *sc = arg;
1136 mii_tick(&sc->sc_mii);
1139 timeout_add_sec(&sc->sc_tick, 1);
1145 struct cpsw_softc * const sc = arg;
1146 struct ifnet * const ifp = &sc->sc_ac.ac_if;
1147 struct cpsw_ring_data * const rdp = sc->sc_rdp;
1153 KASSERT(sc->sc_txrun);
1155 tx0_cp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_CP(0));
1158 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_CP(0), 0xfffffffc);
1159 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_HDP(0), 0);
1160 sc->sc_txrun = false;
1165 tx0_cp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_CP(0));
1166 cpi = (tx0_cp - sc->sc_txdescs_pa) /
1168 KASSERT(sc->sc_txhead < CPSW_NTXDESCS);
1170 cpsw_get_txdesc(sc, sc->sc_txhead, &bd);
1180 printf("pwned %x %x %x\n", cpi, sc->sc_txhead,
1181 sc->sc_txnext);
1186 sc->sc_txrun = false;
1190 bus_dmamap_sync(sc->sc_bdt, rdp->tx_dm[sc->sc_txhead],
1191 0, rdp->tx_dm[sc->sc_txhead]->dm_mapsize,
1193 bus_dmamap_unload(sc->sc_bdt, rdp->tx_dm[sc->sc_txhead]);
1195 m_freem(rdp->tx_mb[sc->sc_txhead]);
1196 rdp->tx_mb[sc->sc_txhead] = NULL;
1205 sc->sc_txeoq = true;
1207 if (sc->sc_txhead == cpi) {
1208 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_CP(0),
1209 cpsw_txdesc_paddr(sc, cpi));
1210 sc->sc_txhead = TXDESC_NEXT(sc->sc_txhead);
1213 sc->sc_txhead = TXDESC_NEXT(sc->sc_txhead);
1214 if (sc->sc_txeoq == true)
1218 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX);
1220 if ((sc->sc_txnext != sc->sc_txhead) && sc->sc_txeoq) {
1221 if (bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_HDP(0)) == 0) {
1222 sc->sc_txeoq = false;
1223 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_HDP(0),
1224 cpsw_txdesc_paddr(sc, sc->sc_txhead));
1228 if (handled && sc->sc_txnext == sc->sc_txhead)
1240 struct cpsw_softc * const sc = arg;
1245 miscstat = bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_WR_C_MISC_STAT(0));
1250 dmastat = bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_DMA_INTSTAT_MASKED);
1253 printf("rxhead %02x\n", sc->sc_rxhead);
1255 stat = bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_DMASTATUS);
1257 stat = bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_HDP(0));
1259 stat = bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_TX_CP(0));
1261 stat = bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_RX_HDP(0));
1263 stat = bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_RX_CP(0));
1268 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_DMA_INTMASK_CLEAR, dmastat);
1269 dmastat = bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_DMA_INTSTAT_MASKED);
1273 bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC);