Lines Matching defs:COMANCHE_BASE
43 #define COMANCHE_BASE 0x180000000L /* 21071-CA Regs */
59 #define COMANCHE_GCR (COMANCHE_BASE + 0x0000) /* General Control */
73 #define COMANCHE_RSVD (COMANCHE_BASE + 0x0020) /* Reserved */
75 #define COMANCHE_ED (COMANCHE_BASE + 0x0040) /* Err & Diag Status */
88 #define COMANCHE_TAGENB (COMANCHE_BASE + 0x0060) /* Tag Enable */
125 #define COMANCHE_ERR_LO (COMANCHE_BASE + 0x0080) /* Error Low Address */
127 #define COMANCHE_ERR_HI (COMANCHE_BASE + 0x00a0) /* Error High Address */
130 #define COMANCHE_LCK_LO (COMANCHE_BASE + 0x00c0) /* LDx_L Low Address */
132 #define COMANCHE_LCK_HI (COMANCHE_BASE + 0x00e0) /* LDx_L High Address */
138 #define COMANCHE_GTIM (COMANCHE_BASE + 0x0200) /* Global Timing */
141 #define COMANCHE_RTIM (COMANCHE_BASE + 0x0220) /* Refresh Timing */
143 #define COMANCHE_VFP (COMANCHE_BASE + 0x0240) /* Video Frame Ptr. */
149 #define COMANCHE_PD_LO (COMANCHE_BASE + 0x0260) /* Pres Detect Low */
151 #define COMANCHE_PD_HI (COMANCHE_BASE + 0x0280) /* Pres Detect High */
156 #define COMANCHE_B0_BAR (COMANCHE_BASE + 0x0800) /* Bank 0 BA */
157 #define COMANCHE_B1_BAR (COMANCHE_BASE + 0x0820) /* Bank 1 BA */
158 #define COMANCHE_B2_BAR (COMANCHE_BASE + 0x0840) /* Bank 2 BA */
159 #define COMANCHE_B3_BAR (COMANCHE_BASE + 0x0860) /* Bank 3 BA */
160 #define COMANCHE_B4_BAR (COMANCHE_BASE + 0x0880) /* Bank 4 BA */
161 #define COMANCHE_B5_BAR (COMANCHE_BASE + 0x08a0) /* Bank 5 BA */
162 #define COMANCHE_B6_BAR (COMANCHE_BASE + 0x08c0) /* Bank 6 BA */
163 #define COMANCHE_B7_BAR (COMANCHE_BASE + 0x08e0) /* Bank 7 BA */
164 #define COMANCHE_B8_BAR (COMANCHE_BASE + 0x0900) /* Bank 8 BA */
170 #define COMANCHE_B0_CR (COMANCHE_BASE + 0x0a00) /* Bank 0 Config */
171 #define COMANCHE_B1_CR (COMANCHE_BASE + 0x0a20) /* Bank 1 Config */
172 #define COMANCHE_B2_CR (COMANCHE_BASE + 0x0a40) /* Bank 2 Config */
173 #define COMANCHE_B3_CR (COMANCHE_BASE + 0x0a60) /* Bank 3 Config */
174 #define COMANCHE_B4_CR (COMANCHE_BASE + 0x0a80) /* Bank 4 Config */
175 #define COMANCHE_B5_CR (COMANCHE_BASE + 0x0aa0) /* Bank 5 Config */
176 #define COMANCHE_B6_CR (COMANCHE_BASE + 0x0ac0) /* Bank 6 Config */
177 #define COMANCHE_B7_CR (COMANCHE_BASE + 0x0ae0) /* Bank 7 Config */
178 #define COMANCHE_B8_CR (COMANCHE_BASE + 0x0b00) /* Bank 8 Config */
190 #define COMANCHE_B0_TRA (COMANCHE_BASE + 0x0c00) /* Bank 0 Timing A */
191 #define COMANCHE_B1_TRA (COMANCHE_BASE + 0x0c20) /* Bank 1 Timing A */
192 #define COMANCHE_B2_TRA (COMANCHE_BASE + 0x0c40) /* Bank 2 Timing A */
193 #define COMANCHE_B3_TRA (COMANCHE_BASE + 0x0c60) /* Bank 3 Timing A */
194 #define COMANCHE_B4_TRA (COMANCHE_BASE + 0x0c80) /* Bank 4 Timing A */
195 #define COMANCHE_B5_TRA (COMANCHE_BASE + 0x0ca0) /* Bank 5 Timing A */
196 #define COMANCHE_B6_TRA (COMANCHE_BASE + 0x0cc0) /* Bank 6 Timing A */
197 #define COMANCHE_B7_TRA (COMANCHE_BASE + 0x0ce0) /* Bank 7 Timing A */
198 #define COMANCHE_B8_TRA (COMANCHE_BASE + 0x0d00) /* Bank 8 Timing A */
210 #define COMANCHE_B0_TRB (COMANCHE_BASE + 0x0e00) /* Bank 0 Timing B */
211 #define COMANCHE_B1_TRB (COMANCHE_BASE + 0x0e20) /* Bank 1 Timing B */
212 #define COMANCHE_B2_TRB (COMANCHE_BASE + 0x0e40) /* Bank 2 Timing B */
213 #define COMANCHE_B3_TRB (COMANCHE_BASE + 0x0e60) /* Bank 3 Timing B */
214 #define COMANCHE_B4_TRB (COMANCHE_BASE + 0x0e80) /* Bank 4 Timing B */
215 #define COMANCHE_B5_TRB (COMANCHE_BASE + 0x0ea0) /* Bank 5 Timing B */
216 #define COMANCHE_B6_TRB (COMANCHE_BASE + 0x0ec0) /* Bank 6 Timing B */
217 #define COMANCHE_B7_TRB (COMANCHE_BASE + 0x0ee0) /* Bank 7 Timing B */
218 #define COMANCHE_B8_TRB (COMANCHE_BASE + 0x0f00) /* Bank 8 Timing B */