Lines Matching defs:add_val
3886 if (GET_CODE (biv->add_val) != CONST_INT)
3893 print_rtl (loop_dump_stream, biv->add_val);
3906 print_rtl (loop_dump_stream, biv->add_val);
3912 basestride += INTVAL (biv1->add_val);
3963 else if (!loop_invariant_p (loop, iv->add_val))
3982 the sum of the BIV's initial value and the GIV's add_val. */
3983 address = copy_rtx (iv->add_val);
4245 rtx add_val = simplify_gen_binary (PLUS, Pmode,
4246 info[i].giv->add_val,
4264 add_val, reg, 0, loop_start);
4302 mode. Find all givs that have the same biv, mult_val, and add_val;
4832 loop_iv_add_mult_emit_before (loop, tv->add_val, v->mult_val,
4838 loop_iv_add_mult_emit_before (loop, tv->add_val, v->mult_val,
4839 v->add_val, v->new_reg,
4847 v->mult_val, v->add_val, v->new_reg);
4924 || GET_CODE (v->add_val) != CONST_INT
4925 || INTVAL (v->add_val) % (align / BITS_PER_UNIT) != 0)
4931 && GET_CODE (v->add_val) == REG
4932 && REG_POINTER (v->add_val))
4934 unsigned int align = REGNO_POINTER_ALIGN (REGNO (v->add_val));
4984 v->mult_val, v->add_val, v->dest_reg);
5013 add_cost = iv_add_mult_cost (bl->biv->add_val, v->mult_val,
5263 && ! product_cheap_p (tv->add_val, v->mult_val))
5503 rtx add_val;
5515 (general_induction_var (loop, SET_SRC (set), &src_reg, &add_val,
5520 &add_val, &mult_val, &ext_val, 0,
5532 &add_val, &mult_val, &ext_val,
5546 record_giv (loop, v, p, src_reg, dest_reg, mult_val, add_val,
5651 rtx add_val;
5657 add_val == 0. However, this leads to lost optimizations when
5661 if (general_induction_var (loop, XEXP (x, 0), &src_reg, &add_val,
5670 add_val, ext_val, benefit, DEST_ADDR,
5732 v->add_val = inc_val;
5815 record_giv (loop, v, insn, src_reg, dest_reg, mult_val, add_val, ext_val,
5822 rtx mult_val, add_val, ext_val;
5836 temp = simplify_rtx (add_val);
5838 && ! (GET_CODE (add_val) == MULT
5840 add_val = temp;
5847 v->add_val = add_val;
5992 /* Record whether the add_val contains a const_int, for later use by
5995 rtx tem = add_val;
6000 else if (CONSTANT_P (add_val))
6251 of biv->add_val and giv->mult_val. In this case, we will
6261 biv->add_val,
6512 i.e. giv = biv * mult_val + add_val.
6525 general_induction_var (loop, x, src_reg, add_val, mult_val, ext_val,
6530 rtx *add_val;
6559 *add_val = x;
6566 *add_val = const0_rtx;
6582 *add_val = XEXP (x, 1);
6589 *add_val = const0_rtx;
6598 if (GET_CODE (*add_val) == USE)
6599 *add_val = XEXP (*add_val, 0);
6605 && GET_CODE (*add_val) == PLUS
6606 && (XEXP (*add_val, 0) == frame_pointer_rtx
6607 || XEXP (*add_val, 1) == frame_pointer_rtx))
6952 v->add_val);
7144 add_val, mult_val, ext_val, last_consec_insn)
7150 rtx *add_val;
7178 v->add_val = *add_val;
7203 add_val, mult_val, ext_val, 0,
7208 add_val, mult_val, ext_val, 0,
7217 v->add_val = *add_val;
7386 add = express_from_1 (g1->add_val, g2->add_val, mult);
7393 rtx g1_add_val = g1->add_val;
7408 add = express_from_1 (g1_add_val, g2->add_val, const1_rtx);
8235 && GET_CODE (bl->biv->add_val) == CONST_INT
8236 && INTVAL (bl->biv->add_val) < 0)
8245 % (-INTVAL (bl->biv->add_val))) == 0)
8272 && INTVAL (bl->biv->add_val) == -1)
8284 else if (GET_CODE (bl->biv->add_val) == CONST_INT
8285 && INTVAL (bl->biv->add_val) > 0)
8440 HOST_WIDE_INT add_val, add_adjust, comparison_val = 0;
8447 add_val = INTVAL (bl->biv->add_val);
8482 of add_val in order to do the loop reversal, so
8483 round up comparison_val to a multiple of add_val.
8486 comparison_val = comparison_val + add_val - 1;
8488 -= (unsigned HOST_WIDE_INT) comparison_val % add_val;
8505 && (! (add_val == 1 && loop->vtop
8511 && ! (((comparison_val - add_val) ^ INTVAL (comparison_value))
8516 add_adjust = add_val;
8520 else if (add_val == 1 && loop->vtop
8531 add_adjust -= add_val;
8539 if (((unsigned HOST_WIDE_INT) comparison_val % add_val) != 0)
8544 if (! no_use_except_counting || add_val != 1)
8564 new_add_val = GEN_INT (-INTVAL (bl->biv->add_val));
8591 GEN_INT (add_val));
8623 bl->biv->add_val = new_add_val;
8941 && v->add_val == const0_rtx
8976 && (GET_CODE (v->add_val) == SYMBOL_REF
8977 || GET_CODE (v->add_val) == LABEL_REF
8978 || GET_CODE (v->add_val) == CONST
8979 || (GET_CODE (v->add_val) == REG
8980 && REG_POINTER (v->add_val))))
8991 new = gen_rtx_COMPARE (VOIDmode, copy_rtx (v->add_val),
8995 copy_rtx (v->add_val));
8998 update_reg_last_use (v->add_val, insn);
9008 copy_rtx (v->add_val)));
9035 mult_val and constant add_val. We might be able to support
9041 && (GET_CODE (v->add_val) == SYMBOL_REF
9042 || GET_CODE (v->add_val) == LABEL_REF
9043 || GET_CODE (v->add_val) == CONST
9044 || (GET_CODE (v->add_val) == REG
9045 && REG_POINTER (v->add_val)))
9056 rtx add_val;
9058 if (GET_CODE (v->add_val) == CONST_INT)
9059 add_val = v->add_val;
9061 add_val = const0_rtx;
9064 add_val, mode, 1))
9078 && GET_CODE (v->add_val) == CONST_INT)
9081 v->add_val, mode, 1);
9088 v->mult_val, v->add_val,
9098 /* Look for giv with positive constant mult_val and nonconst add_val.
9125 v->mult_val, v->add_val,
9138 add_val. Insert insns to compute new compare value.
9163 v->mult_val, v->add_val,
9202 && rtx_equal_p (tv->add_val, v->add_val)
10855 print_simple_rtl (file, v->add_val);
10886 print_simple_rtl (file, v->add_val);
10950 print_simple_rtl (file, v->add_val);