gas/config/tc-i386.c

146     union i386_op op[MAX_OPERANDS];
466   /* Various efficient no-op patterns for aligning code labels.
1049 	fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1051 	pe (x->op[i].imms);
1053 	pe (x->op[i].disps);
1397 	    if (i.op[x].regs->reg_num != x)
1399 			i.op[x].regs->reg_name, x + 1, i.tm.name);
1411       i.op[i.operands].imms = exp;
1431   if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1438       && i.op[0].disps->X_op == O_constant)
1443       i.op[0].disps->X_add_symbol = &abs_symbol;
1444       i.op[0].disps->X_op = O_symbol;
1455        && (i.op[0].regs->reg_flags & RegRex64) != 0)
1457 	  && (i.op[1].regs->reg_flags & RegRex64) != 0)
1468 	      && (i.op[x].regs->reg_flags & RegRex64) == 0)
1471 	      if (i.op[x].regs->reg_num > 3)
1473 			i.op[x].regs->reg_name);
1479 	      i.op[x].regs = i.op[x].regs + 8;
1809   temp_op = i.op[xchg2];
1810   i.op[xchg2] = i.op[xchg1];
1811   i.op[xchg1] = temp_op;
1831   int op;
1841       for (op = i.operands; --op >= 0;)
1842 	if (i.types[op] & Reg)
1844 	    if (i.types[op] & Reg8)
1846 	    else if (i.types[op] & Reg16)
1848 	    else if (i.types[op] & Reg32)
1850 	    else if (i.types[op] & Reg64)
1858   for (op = i.operands; --op >= 0;)
1859     if (i.types[op] & Imm)
1861 	switch (i.op[op].imms->X_op)
1868 		i.types[op] |= Imm32 | Imm64;
1871 		i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1874 		i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1883 	    if ((i.types[op] & Imm16)
1884 		&& (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
1886 		i.op[op].imms->X_add_number =
1887 		  (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1889 	    if ((i.types[op] & Imm32)
1890 		&& ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1893 		i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1897 	    i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
1902 	      i.types[op] &= ~Imm32;
1915 		i.types[op] = Imm64 | Imm32S;
1918 		i.types[op] = Imm32;
1921 		i.types[op] = Imm16;
1924 		i.types[op] = Imm8 | Imm8S;
1936   int op;
1938   for (op = i.operands; --op >= 0;)
1939     if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
1941 	offsetT disp = i.op[op].disps->X_add_number;
1943 	if (i.types[op] & Disp16)
1952 	else if (i.types[op] & Disp32)
1963 	      i.types[op] |= Disp32S;
1965 	      i.types[op] |= Disp32;
1967 	if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1969 	  i.types[op] |= Disp8;
2212 	  int op;
2214 	  for (op = i.operands; --op >= 0;)
2215 	    if ((i.types[op] & Reg)
2216 		&& !(i.tm.operand_types[op] & InOutPortReg))
2218 		i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2219 			    (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2220 			    (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2314   int op;
2316   for (op = i.operands; --op >= 0;)
2321       if (i.types[op] & Reg8)
2333       if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2338 	  && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2345 	      && (i.tm.operand_types[op] & InOutPortReg) == 0)
2348 		      i.op[op].regs->reg_name,
2354 	      && (i.tm.operand_types[op] & InOutPortReg) == 0)
2356 		     (i.op[op].regs + (i.types[op] & Reg16
2359 		     i.op[op].regs->reg_name,
2365       if (i.types[op] & (Reg | RegMMX | RegXMM
2371 		  i.op[op].regs->reg_name,
2383   int op;
2385   for (op = i.operands; --op >= 0;)
2388     if ((i.types[op] & Reg8) != 0
2389 	&& (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2392 		i.op[op].regs->reg_name,
2399 	     && (i.types[op] & Reg16) != 0
2400 	     && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2407 		    i.op[op].regs->reg_name,
2414 		   (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2415 		   i.op[op].regs->reg_name,
2420     else if ((i.types[op] & Reg64) != 0
2421 	     && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2424 		i.op[op].regs->reg_name,
2434   int op;
2436   for (op = i.operands; --op >= 0; )
2439     if ((i.types[op] & Reg8) != 0
2440 	&& (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2443 		i.op[op].regs->reg_name,
2449     else if (((i.types[op] & Reg16) != 0
2450 	      || (i.types[op] & Reg32) != 0)
2451 	     && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2456 		i.op[op].regs->reg_name,
2466   int op;
2467   for (op = i.operands; --op >= 0;)
2470     if ((i.types[op] & Reg8) != 0
2471 	&& (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2474 		i.op[op].regs->reg_name,
2481 	     && (i.types[op] & Reg32) != 0
2482 	     && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
2489 		    i.op[op].regs->reg_name,
2496 		   (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2497 		   i.op[op].regs->reg_name,
2597       assert (i.op[first_reg_op + 1].regs == 0);
2598       i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2606       unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2608       i.tm.base_opcode |= i.op[op].regs->reg_num;
2609       if ((i.op[op].regs->reg_flags & RegRex) != 0)
2619 		       i.op[1].regs->reg_name,
2620 		       i.op[0].regs->reg_name);
2626 		       i.op[0].regs->reg_name);
2641 	  && i.op[0].regs->reg_num == 1)
2646       i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2647       if ((i.op[0].regs->reg_flags & RegRex) != 0)
2703 	  i.rm.reg = i.op[dest].regs->reg_num;
2704 	  i.rm.regmem = i.op[source].regs->reg_num;
2705 	  if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2707 	  if ((i.op[source].regs->reg_flags & RegRex) != 0)
2712 	  i.rm.reg = i.op[source].regs->reg_num;
2713 	  i.rm.regmem = i.op[dest].regs->reg_num;
2714 	  if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2716 	  if ((i.op[source].regs->reg_flags & RegRex) != 0)
2725 	  unsigned int op = ((i.types[0] & AnyMem)
2748 		      i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
2753 		      i.types[op] = Disp16;
2758 		      i.types[op] = Disp32;
2767 		  i.types[op] &= ~Disp;
2769 		    i.types[op] |= Disp32;	/* Must be 32 bit */
2771 		    i.types[op] |= Disp32S;
2780 	      i.types[op] &= ~ Disp;
2781 	      i.types[op] |= Disp32S;
2782 	      i.flags[op] = Operand_PCrel;
2801 		      if ((i.types[op] & Disp) == 0)
2804 			  i.types[op] |= Disp8;
2814 	      i.rm.mode = mode_from_disp_size (i.types[op]);
2819 		  && (i.types[op] & Disp))
2820 		i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
2834 		      i.types[op] |= Disp8;
2863 	      i.rm.mode = mode_from_disp_size (i.types[op]);
2868 	      /* Fakes a zero displacement assuming that i.types[op]
2872 	      assert (i.op[op].disps == 0);
2874 	      i.op[op].disps = exp;
2888 	  unsigned int op =
2904 	      i.rm.regmem = i.op[op].regs->reg_num;
2905 	      if ((i.op[op].regs->reg_flags & RegRex) != 0)
2910 	      i.rm.reg = i.op[op].regs->reg_num;
2911 	      if ((i.op[op].regs->reg_flags & RegRex) != 0)
2991   sym = i.op[0].disps->X_add_symbol;
2992   off = i.op[0].disps->X_add_number;
2994   if (i.op[0].disps->X_op != O_constant
2995       && i.op[0].disps->X_op != O_symbol)
2998       sym = make_expr_symbol (i.op[0].disps);
3064 		      i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3115   if (i.op[1].imms->X_op == O_constant)
3117       offsetT n = i.op[1].imms->X_add_number;
3130 		 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3131   if (i.op[0].imms->X_op != O_constant)
3134   md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3283 	  if (i.op[n].disps->X_op == O_constant)
3297 	      val = offset_in_range (i.op[n].disps->X_add_number,
3333 		  i.op[n].disps->X_add_number -= imm_size;
3350 		  && GOT_symbol == i.op[n].disps->X_add_symbol
3351 		  && (i.op[n].disps->X_op == O_symbol
3352 		      || (i.op[n].disps->X_op == O_add
3354 			       (i.op[n].disps->X_op_symbol)->X_op)
3376 		  i.op[n].disps->X_add_number += add;
3379 			   i.op[n].disps, pcrel, reloc_type);
3397 	  if (i.op[n].imms->X_op == O_constant)
3411 	      val = offset_in_range (i.op[n].imms->X_add_number,
3485 		  && GOT_symbol == i.op[n].imms->X_add_symbol
3486 		  && (i.op[n].imms->X_op == O_symbol
3487 		      || (i.op[n].imms->X_op == O_add
3489 			       (i.op[n].imms->X_op_symbol)->X_op)
3511 		  i.op[n].imms->X_add_number += add;
3514 			   i.op[n].imms, 0, reloc_type);
3688   i.op[this_operand].imms = exp;
3828   i.op[this_operand].disps = exp;
4127       i.op[this_operand].regs = r;
4300       /* Special case for (%dx) while doing input/output op.  */
5941 	  i.op[this_operand].regs = reg;