Target/Sparc/DelaySlotFiller.cpp

116         (MI->getOpcode() == SP::RESTORErr
117          || MI->getOpcode() == SP::RESTOREri)) {
125         (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD
126          || MI->getOpcode() == SP::FCMPQ)) {
127       BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
145       BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
155               TII->get(SP::UNIMP)).addImm(structSize);
179   if (Opc == SP::RET || Opc == SP::TLS_CALL)
182   if (Opc == SP::RETL || Opc == SP::TAIL_CALL || Opc == SP::TAIL_CALLri) {
186     if (J->getOpcode() == SP::RESTORErr
187         || J->getOpcode() == SP::RESTOREri) {
189       if (Opc == SP::RETL)
190         slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET));
277       Opcode >=  SP::LDDArr && Opcode <= SP::LDrr)
283       Opcode >=  SP::FDIVD && Opcode <= SP::FSQRTD)
296   RegDefs.insert(SP::O7);
300   case SP::CALL: break;
301   case SP::CALLrr:
302   case SP::CALLri:
336       if (MO.isImplicit() && MI->getOpcode() == SP::RETL)
362   case SP::CALL: structSizeOpNum = 1; break;
363   case SP::CALLrr:
364   case SP::CALLri: structSizeOpNum = 2; break;
365   case SP::TLS_CALL: return false;
366   case SP::TAIL_CALLri:
367   case SP::TAIL_CALL: return false;
387   if (reg < SP::I0 || reg > SP::I7)
394   AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr)
395                           ? SP::RESTORErr
396                           : SP::RESTOREri));
399   AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
415   if (reg < SP::I0 || reg > SP::I7)
419   if (OrMI->getOpcode() == SP::ORrr
420       && OrMI->getOperand(1).getReg() != SP::G0
421       && OrMI->getOperand(2).getReg() != SP::G0)
424   if (OrMI->getOpcode() == SP::ORri
425       && OrMI->getOperand(1).getReg() != SP::G0
433   OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr)
434                          ? SP::RESTORErr
435                          : SP::RESTOREri));
438   OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
453   if (reg < SP::I0 || reg > SP::I7)
468   assert(RestoreMI->getOpcode() == SP::RESTORErr);
470   RestoreMI->setDesc(TII->get(SP::RESTOREri));
472   RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
473   RestoreMI->getOperand(1).setReg(SP::G0);
491   assert(MBBI->getOpcode() == SP::RESTORErr
492          && MBBI->getOperand(0).getReg() == SP::G0
493          && MBBI->getOperand(1).getReg() == SP::G0
494          && MBBI->getOperand(2).getReg() == SP::G0);
506   case SP::ADDrr:
507   case SP::ADDri: return combineRestoreADD(MBBI, PrevInst, TII); break;
508   case SP::ORrr:
509   case SP::ORri:  return combineRestoreOR(MBBI, PrevInst, TII); break;
510   case SP::SETHIi: return combineRestoreSETHIi(MBBI, PrevInst, TII); break;