Target/ARM/ARMExpandPseudoInsts.cpp

131     assert(MO.isReg() && MO.getReg());
519     assert(llvm::is_sorted(NEONLdStTable) && "NEONLdStTable is not sorted!");
557     assert(RegSpc == OddDblSpc && "unknown register spacing");
573   assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
599       assert(RegSpc == OddDblSpc && "Unexpected spacing!");
646       assert(AM6Offset.getReg() == 0 &&
694   assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
725       assert(AM6Offset.getReg() == 0 &&
770   assert(TableEntry && "NEONLdStTable lookup failed");
783   assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
788   assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
989     assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
991     assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
1223       assert(Reg.isPhysical() && "Unallocated register");
1347   assert(!ScratchRegs.empty());
1362       assert(!ARM::DPRRegClass.contains(Reg) ||
1364       assert(!ARM::QPRRegClass.contains(Reg));
1399     assert(STI->hasFPRegs() && "Subtarget needs fpregs");
1549       assert(!ARM::DPRRegClass.contains(Reg) ||
1551       assert(!ARM::QPRRegClass.contains(Reg));
1586     assert(STI->hasFPRegs() && "Subtarget needs fpregs");
1731   assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
1737     assert(STI->hasV8MBaselineOps() &&
1739     assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) &&
1741     assert((UxtOp == 0 || ARM::tGPRRegClass.contains(DesiredReg)) &&
1854   assert(!STI->isThumb1Only() && "CMP_SWAP_64 unsupported under Thumb1!");
1861   assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
2119       assert(MBBI->isReturn() &&
2149           assert(JumpTarget.isSymbol());
2200       assert(llvm::all_of(MBBI->operands(), [](const MachineOperand &Op) {
2420         assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
2438           assert (!AFI->isThumb1OnlyFunction());
2440           assert(MaxAlign <= Align(256) &&
3044       assert(STI->isThumb());
3048       assert(STI->isThumb());
3052       assert(STI->isThumb());
3056       assert(!STI->isThumb());
3060       assert(!STI->isThumb());
3064       assert(!STI->isThumb());
3074       assert(Reg == ARM::LR && "expect LR register!");