Target/AMDGPU/R600MachineScheduler.cpp

53   SUnit *SU = nullptr;
93   if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
96     SU = pickAlu();
97     if (!SU && !PhysicalRegCopy.empty()) {
98       SU = PhysicalRegCopy.front();
101     if (SU) {
108   if (!SU) {
110     SU = pickOther(IDFetch);
111     if (SU)
116   if (!SU) {
117     SU = pickOther(IDOther);
118     if (SU)
122   LLVM_DEBUG(if (SU) {
124     DAG->dumpNode(*SU);
132   return SU;
135 void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {
146     switch (getAluKind(SU)) {
154       for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(),
155           E = SU->getInstr()->operands_end(); It != E; ++It) {
182 void R600SchedStrategy::releaseTopNode(SUnit *SU) {
183   LLVM_DEBUG(dbgs() << "Top Releasing "; DAG->dumpNode(*SU));
186 void R600SchedStrategy::releaseBottomNode(SUnit *SU) {
187   LLVM_DEBUG(dbgs() << "Bottom Releasing "; DAG->dumpNode(*SU));
188   if (isPhysicalRegCopy(SU->getInstr())) {
189     PhysicalRegCopy.push_back(SU);
193   int IK = getInstKind(SU);
197     Available[IDOther].push_back(SU);
199     Pending[IK].push_back(SU);
212 R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const {
213   MachineInstr *MI = SU->getInstr();
286 int R600SchedStrategy::getInstKind(SUnit* SU) {
287   int Opcode = SU->getInstr()->getOpcode();
315     SUnit *SU = *It;
316     InstructionsGroupCandidate.push_back(SU->getInstr());
318         (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) {
321       return SU;
331   for (SUnit *SU : QSrc) {
332     AluKind AK = getAluKind(SU);
333     AvailableAlus[AK].push_back(SU);
424       SUnit *SU = AttemptFillSlot(3, true);
425       if (SU) {
427         return SU;
433         SUnit *SU = AttemptFillSlot(Chan, false);
434         if (SU) {
436           InstructionsGroupCandidate.push_back(SU->getInstr());
437           return SU;
447   SUnit *SU = nullptr;
454     SU = AQ.back();
457   return SU;