Lines Matching defs:SRA
1244 setOperationAction(ISD::SRA, VT, Custom);
1581 setOperationAction(ISD::SRA, VT, Custom);
1783 setOperationAction(ISD::SRA, VT, Custom);
1907 setOperationAction(ISD::SRA, VT, Custom);
3407 if (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA)
3612 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
5927 case ISD::SRA:
9024 DAG.getNode(ISD::SRA, dl, VT, LHS,
12992 case ISD::SRA:
12997 unsigned Opc = Op.getOpcode() == ISD::SRA ? AArch64ISD::SRA_PRED
13005 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
13013 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
14932 assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
15303 SDValue SRA =
15304 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
15309 return SRA;
15311 Created.push_back(SRA.getNode());
15312 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
17539 } else if (Opcode == ISD::SHL || Opcode == ISD::SRL || Opcode == ISD::SRA) {
20052 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
20464 case ISD::SRA:
20595 auto Shift = DAG.getNode(ISD::SRA, SDLoc(N), VT, CmpLHS, Val);