src/shared/nicpci.c

513 	uint32 reg_val;
520 	reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
531 		reg_val &= ~PCIE_CAP_DEVCTRL_MRRS_MASK;
532 		reg_val |= (val << PCIE_CAP_DEVCTRL_MRRS_SHIFT) & PCIE_CAP_DEVCTRL_MRRS_MASK;
534 		OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), reg_val);
535 		reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
537 	return reg_val;
544 	uint32 reg_val;
551 	reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
554 		reg_val &= ~PCIE_CAP_DEVCTRL_MPS_MASK;
555 		reg_val |= (val << PCIE_CAP_DEVCTRL_MPS_SHIFT) & PCIE_CAP_DEVCTRL_MPS_MASK;
557 		OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), reg_val);
558 		reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
560 	return reg_val;
567 	uint32 reg_val;
574 	reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
578 			reg_val |= PCIE_CLKREQ_ENAB;
580 			reg_val &= ~PCIE_CLKREQ_ENAB;
581 		OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), reg_val);
582 		reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
584 	if (reg_val & PCIE_CLKREQ_ENAB)
594 	uint32 reg_val;
601 	reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
606 			reg_val |= PCIE_CAP_DEVCTRL2_LTR_ENAB_MASK;
608 			reg_val &= ~PCIE_CAP_DEVCTRL2_LTR_ENAB_MASK;
609 		OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), reg_val);
610 		reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
612 	if (reg_val & PCIE_CAP_DEVCTRL2_LTR_ENAB_MASK)
629 	uint32 reg_val;
636 	reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
640 		reg_val = (reg_val & ~PCIE_CAP_DEVCTRL2_OBFF_ENAB_MASK) |
643 		OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), reg_val);
644 		reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32));
647 	return  (reg_val & PCIE_CAP_DEVCTRL2_OBFF_ENAB_MASK) >> PCIE_CAP_DEVCTRL2_OBFF_ENAB_SHIFT;
654 	uint32 reg_val;
676 		reg_val = val;
677 		pcie_writereg(pi->sih, pi->regs.pcieregs, PCIE_CONFIGREGS, offset, reg_val);
680 		reg_val = pcie_readreg(pi->sih, pi->regs.pcieregs, PCIE_CONFIGREGS, offset);
683 	return reg_val;
1558 	uint32 reg_val = 0;
1570 		return reg_val;
1572 	reg_val = pcie_readreg(pi->sih, pcieregs, type, offset);
1573 	PCI_ERROR(("PCIEREG: 0x%x readval is 0x%x\n", offset, reg_val));
1575 	return reg_val;
1581 	uint32 reg_val = 0;
1588 	if (pcie_mdioread(pi, mdioslave, offset, &reg_val))
1589 		reg_val = 0xFFFFFFFF;
1591 	return reg_val;
1787 	uint reg_val = 0;
1825 		pcie_mdioread(pi, MDIO_DEV_IEEE0, 0x2, &reg_val);
1826 		bcm_bprintf(b, "block IEEE0, offset 2: 0x%x\n", reg_val);
1827 		pcie_mdioread(pi, MDIO_DEV_IEEE0, 0x3, &reg_val);
1828 		bcm_bprintf(b, "block IEEE0, offset 2: 0x%x\n", reg_val);
1829 		pcie_mdioread(pi, MDIO_DEV_IEEE1, 0x08, &reg_val);
1830 		bcm_bprintf(b, "block IEEE1, lanestatus: 0x%x\n", reg_val);
1831 		pcie_mdioread(pi, MDIO_DEV_IEEE1, 0x0a, &reg_val);
1832 		bcm_bprintf(b, "block IEEE1, lanestatus2: 0x%x\n", reg_val);
1833 		pcie_mdioread(pi, MDIO_DEV_BLK4, 0x16, &reg_val);
1834 		bcm_bprintf(b, "MDIO_DEV_BLK4, lanetest0: 0x%x\n", reg_val);
1835 		pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x11, &reg_val);
1836 		bcm_bprintf(b, "MDIO_DEV_TXPLL, pllcontrol: 0x%x\n", reg_val);
1837 		pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x12, &reg_val);
1838 		bcm_bprintf(b, "MDIO_DEV_TXPLL, plltimer1: 0x%x\n", reg_val);
1839 		pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x13, &reg_val);
1840 		bcm_bprintf(b, "MDIO_DEV_TXPLL, plltimer2: 0x%x\n", reg_val);
1841 		pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x14, &reg_val);
1842 		bcm_bprintf(b, "MDIO_DEV_TXPLL, plltimer3: 0x%x\n", reg_val);
1843 		pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x17, &reg_val);
1844 		bcm_bprintf(b, "MDIO_DEV_TXPLL, freqdetcounter: 0x%x\n", reg_val);
1846 		pcie_mdioread(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, &reg_val);
1847 		bcm_bprintf(b, "rxtimer1 0x%x ", reg_val);
1848 		pcie_mdioread(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, &reg_val);
1849 		bcm_bprintf(b, "rxCDR 0x%x ", reg_val);
1850 		pcie_mdioread(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, &reg_val);
1851 		bcm_bprintf(b, "rxCDRBW 0x%x\n", reg_val);