Lines Matching defs:pcieregs
37 sbpcieregs_t *pcieregs;
153 pi->regs.pcieregs = (sbpcieregs_t*)regs;
163 pi->regs.pcieregs = (sbpcieregs_t*)regs;
251 pcie_readreg(si_t *sih, sbpcieregs_t *pcieregs, uint addrtype, uint offset)
256 ASSERT(pcieregs != NULL);
262 W_REG(osh, (&pcieregs->configaddr), offset);
263 (void)R_REG(osh, (&pcieregs->configaddr));
264 retval = R_REG(osh, &(pcieregs->configdata));
267 W_REG(osh, &(pcieregs->u.pcie1.pcieindaddr), offset);
268 (void)R_REG(osh, (&pcieregs->u.pcie1.pcieindaddr));
269 retval = R_REG(osh, &(pcieregs->u.pcie1.pcieinddata));
277 W_REG(osh, (&pcieregs->configaddr), offset);
278 (void)R_REG(osh, (&pcieregs->configaddr));
279 retval = R_REG(osh, &(pcieregs->configdata));
286 pcie_writereg(si_t *sih, sbpcieregs_t *pcieregs, uint addrtype, uint offset, uint val)
290 ASSERT(pcieregs != NULL);
296 W_REG(osh, (&pcieregs->configaddr), offset);
297 W_REG(osh, (&pcieregs->configdata), val);
300 W_REG(osh, (&pcieregs->u.pcie1.pcieindaddr), offset);
301 W_REG(osh, (&pcieregs->u.pcie1.pcieinddata), val);
309 W_REG(osh, (&pcieregs->configaddr), offset);
310 W_REG(osh, (&pcieregs->configdata), val);
318 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
324 W_REG(pi->osh, &pcieregs->u.pcie1.mdiodata, mdiodata);
329 if (R_REG(pi->osh, &(pcieregs->u.pcie1.mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
347 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
352 W_REG(pi->osh, &pcieregs->u.pcie2.mdiocontrol, mdioctrl);
355 W_REG(pi->osh, &pcieregs->u.pcie2.mdiowrdata, mdiodata);
360 if (!(R_REG(pi->osh, &(pcieregs->u.pcie2.mdiowrdata)) & MDIODATA2_DONE)) {
390 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
409 W_REG(pi->osh, (&pcieregs->u.pcie2.mdiocontrol), mdio_ctrl);
411 reg32 = (uint32 *)&(pcieregs->u.pcie2.mdiowrdata);
415 reg32 = (uint32 *)&(pcieregs->u.pcie2.mdiorddata);
433 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
442 W_REG(pi->osh, (&pcieregs->u.pcie1.mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
461 W_REG(pi->osh, &pcieregs->u.pcie1.mdiodata, mdiodata);
467 if (R_REG(pi->osh, &(pcieregs->u.pcie1.mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
470 *val = (R_REG(pi->osh, &(pcieregs->u.pcie1.mdiodata)) &
474 W_REG(pi->osh, (&pcieregs->u.pcie1.mdiocontrol), 0);
483 W_REG(pi->osh, (&pcieregs->u.pcie1.mdiocontrol), 0);
677 pcie_writereg(pi->sih, pi->regs.pcieregs, PCIE_CONFIGREGS, offset, reg_val);
680 reg_val = pcie_readreg(pi->sih, pi->regs.pcieregs, PCIE_CONFIGREGS, offset);
691 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
697 ASSERT(pcieregs != NULL);
701 W_REG(pi->osh, &(pcieregs->ltrspacing), val);
704 retval = R_REG(pi->osh, &(pcieregs->ltrspacing));
715 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
721 ASSERT(pcieregs != NULL);
725 W_REG(pi->osh, &(pcieregs->ltrhysteresiscnt), val);
728 retval = R_REG(pi->osh, &(pcieregs->ltrhysteresiscnt));
739 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
744 w = pcie_readreg(sih, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
750 pcie_writereg(sih, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG, w);
751 w = pcie_readreg(sih, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
805 w = pcie_readreg(pi->sih, pi->regs.pcieregs, PCIE_PCIEREGS, PCIE_PLP_STATUSREG);
825 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
836 reg16 = &pcieregs->sprom[SRSH_ASPM_OFFSET];
855 reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET_REV5];
870 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
876 reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET_REV8];
910 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
913 reg16 = &pcieregs->sprom[SRSH_PCIE_MISC_CONFIG];
926 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
936 reg16 = &pcieregs->sprom[SRSH_BD_OFFSET];
945 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
949 w = pcie_readreg(sih, pcieregs, PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG);
951 pcie_writereg(sih, pcieregs, PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG, w);
955 w = pcie_readreg(sih, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG);
957 pcie_writereg(sih, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w);
966 w = pcie_readreg(sih, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
969 pcie_writereg(sih, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG, w);
1156 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1165 data = pcie_readreg(sih, pcieregs, PCIE_CONFIGREGS, PCIECFGREG_PDL_CTRL1);
1166 pcie_writereg(pch, pcieregs, PCIE_CONFIGREGS,
1177 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1183 pcie_writereg(pch, pcieregs, PCIE_CONFIGREGS, PCIECFGREG_REG_PHY_CTL7, 0);
1185 pcie_writereg(pch, pcieregs, PCIE_CONFIGREGS, PCIECFGREG_REG_PHY_CTL7, 0x14031);
1187 pcie_writereg(pch, pcieregs, PCIE_CONFIGREGS, PCIECFGREG_REG_PHY_CTL7, 0x2c031);
1195 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1203 data = pcie_readreg(sih, pcieregs, PCIE_CONFIGREGS, pi->pciecap_lcreg_offset);
1204 pcie_writereg(sih, pcieregs, PCIE_CONFIGREGS, pi->pciecap_lcreg_offset, data | 2);
1422 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1432 reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET_REV8];
1560 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1564 pcie_writereg(pi->sih, pcieregs, type, offset, val);
1572 reg_val = pcie_readreg(pi->sih, pcieregs, type, offset);
1653 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1656 data = pcie_readreg(pi->sih, pcieregs, PCIE_CONFIGREGS, pi->pciecap_lcreg_offset);
1665 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1670 w = (R_REG(pi->osh, (&pcieregs->control)) & ~mask) | val;
1671 W_REG(pi->osh, (&pcieregs->control), w);
1674 return R_REG(pi->osh, (&pcieregs->control));
1785 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
1821 W_REG(pi->osh, (&pcieregs->u.pcie1.mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
1855 W_REG(pi->osh, (&pcieregs->u.pcie1.mdiocontrol), 0);