Lines Matching defs:pch
85 static void pcicore_fixlatencytimer(pcicore_info_t* pch, uint8 timer_val);
180 pcicore_deinit(void *pch)
182 pcicore_info_t *pi = (pcicore_info_t *)pch;
510 pcie_devcontrol_mrrs(void *pch, uint32 mask, uint32 val)
512 pcicore_info_t *pi = (pcicore_info_t *)pch;
541 pcie_devcontrol_mps(void *pch, uint32 mask, uint32 val)
543 pcicore_info_t *pi = (pcicore_info_t *)pch;
564 pcie_clkreq(void *pch, uint32 mask, uint32 val)
566 pcicore_info_t *pi = (pcicore_info_t *)pch;
591 pcie_ltrenable(void *pch, uint32 mask, uint32 val)
593 pcicore_info_t *pi = (pcicore_info_t *)pch;
626 pcie_obffenable(void *pch, uint32 mask, uint32 val)
628 pcicore_info_t *pi = (pcicore_info_t *)pch;
651 pcie_ltr_reg(void *pch, uint32 reg, uint32 mask, uint32 val)
653 pcicore_info_t *pi = (pcicore_info_t *)pch;
687 pcieltrspacing_reg(void *pch, uint32 mask, uint32 val)
689 pcicore_info_t *pi = (pcicore_info_t *)pch;
711 pcieltrhysteresiscnt_reg(void *pch, uint32 mask, uint32 val)
713 pcicore_info_t *pi = (pcicore_info_t *)pch;
983 pcie_war_ovr_aspm_update(void *pch, uint8 aspm)
985 pcicore_info_t *pi = (pcicore_info_t *)pch;
1005 pcie_power_save_enable(void *pch, bool enable)
1007 pcicore_info_t *pi = (pcicore_info_t *)pch;
1046 pcie_set_request_size(void *pch, uint16 size)
1048 pcicore_info_t *pi = (pcicore_info_t *)pch;
1080 pcie_get_request_size(void *pch)
1082 pcicore_info_t *pi = (pcicore_info_t *)pch;
1097 pcie_set_maxpayload_size(void *pch, uint16 size)
1099 pcicore_info_t *pi = (pcicore_info_t *)pch;
1119 pcie_get_maxpayload_size(void *pch)
1121 pcicore_info_t *pi = (pcicore_info_t *)pch;
1138 pcie_disable_TL_clk_gating(void *pch)
1141 pcicore_info_t *pi = (pcicore_info_t *)pch;
1151 pcie_set_L1_entry_time(void *pch, uint32 val)
1154 pcicore_info_t *pi = (pcicore_info_t *)pch;
1166 pcie_writereg(pch, pcieregs, PCIE_CONFIGREGS,
1172 pcie_set_error_injection(void *pch, uint32 mode)
1175 pcicore_info_t *pi = (pcicore_info_t *)pch;
1183 pcie_writereg(pch, pcieregs, PCIE_CONFIGREGS, PCIECFGREG_REG_PHY_CTL7, 0);
1185 pcie_writereg(pch, pcieregs, PCIE_CONFIGREGS, PCIECFGREG_REG_PHY_CTL7, 0x14031);
1187 pcie_writereg(pch, pcieregs, PCIE_CONFIGREGS, PCIECFGREG_REG_PHY_CTL7, 0x2c031);
1191 pcie_set_L1substate(void *pch, uint32 substate)
1193 pcicore_info_t *pi = (pcicore_info_t *)pch;
1207 pcie_ltrenable(pch, 1, 1);
1224 pcie_get_L1substate(void *pch)
1226 pcicore_info_t *pi = (pcicore_info_t *)pch;
1247 BCMATTACHFN(pcicore_attach)(void *pch, char *pvars, int state)
1249 pcicore_info_t *pi = (pcicore_info_t *)pch;
1294 pcicore_pcieserdesreg(pch, MDIO_DEV_TXCTRL0, 0x18, 0xff, 0x7f);
1297 pcicore_pcieserdesreg(pch, MDIO_DEV_TXCTRL0, 0x18, 0xff, 0x70);
1302 pcicore_hwup(void *pch)
1304 pcicore_info_t *pi = (pcicore_info_t *)pch;
1312 pcicore_fixlatencytimer(pch, 0x20);
1320 pcicore_pcieserdesreg(pch, MDIO_DEV_TXCTRL0, 0x18, 0xff, 0x7f);
1323 pcicore_pcieserdesreg(pch, MDIO_DEV_TXCTRL0, 0x18, 0xff, 0x70);
1328 pcicore_up(void *pch, int state)
1330 pcicore_info_t *pi = (pcicore_info_t *)pch;
1356 pcicore_sleep(void *pch)
1358 pcicore_info_t *pi = (pcicore_info_t *)pch;
1380 pcicore_down(void *pch, int state)
1382 pcicore_info_t *pi = (pcicore_info_t *)pch;
1446 pcicore_pmeen(void *pch)
1448 pcicore_info_t *pi = (pcicore_info_t *)pch;
1464 pcicore_pmestat(void *pch)
1466 pcicore_info_t *pi = (pcicore_info_t *)pch;
1478 pcicore_pmestatclr(void *pch)
1480 pcicore_info_t *pi = (pcicore_info_t *)pch;
1500 pcicore_pmeclr(void *pch)
1502 pcicore_info_t *pi = (pcicore_info_t *)pch;
1521 pcicore_fixlatencytimer(pcicore_info_t* pch, uint8 timer_val)
1523 pcicore_info_t *pi = (pcicore_info_t *)pch;
1538 pcie_lcreg(void *pch, uint32 mask, uint32 val)
1540 pcicore_info_t *pi = (pcicore_info_t *)pch;
1556 pcicore_pciereg(void *pch, uint32 offset, uint32 mask, uint32 val, uint type)
1559 pcicore_info_t *pi = (pcicore_info_t *)pch;
1579 pcicore_pcieserdesreg(void *pch, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val)
1582 pcicore_info_t *pi = (pcicore_info_t *)pch;
1595 pcie_get_ssid(void* pch)
1598 OSL_PCI_READ_CONFIG(((pcicore_info_t *)pch)->osh, PCI_CFG_SVID, sizeof(uint32));
1603 pcie_get_bar0(void* pch)
1605 return OSL_PCI_READ_CONFIG(((pcicore_info_t *)pch)->osh, PCI_CFG_BAR0, sizeof(uint32));
1609 pcie_configspace_cache(void* pch)
1611 pcicore_info_t *pi = (pcicore_info_t *)pch;
1623 pcie_configspace_restore(void* pch)
1625 pcicore_info_t *pi = (pcicore_info_t *)pch;
1642 pcie_configspace_get(void* pch, uint8 *buf, uint size)
1644 pcicore_info_t *pi = (pcicore_info_t *)pch;
1650 pcie_get_link_speed(void* pch)
1652 pcicore_info_t *pi = (pcicore_info_t *)pch;
1661 pcie_survive_perst(void* pch, uint32 mask, uint32 val)
1664 pcicore_info_t *pi = (pcicore_info_t *)pch;
1763 pcicore_dump_pcieinfo(void *pch, struct bcmstrbuf *b)
1765 pcicore_info_t *pi = (pcicore_info_t *)pch;
1770 bcm_bprintf(b, "PCIE link speed: %d\n", pcie_get_link_speed(pch));
1782 pcicore_dump_pcieregs(void *pch, struct bcmstrbuf *b)
1784 pcicore_info_t *pi = (pcicore_info_t *)pch;