Lines Matching refs:uint32
33 uint32 g_assert_type = 0;
42 _change_cachability(uint32 cm)
44 uint32 prid, c0reg;
58 static void (*change_cachability)(uint32);
63 uint32 config, config1, r2, tmp;
87 tmp = R_REG(NULL, (uint32 *)(OSL_UNCACHED(SI_ENUM_BASE + CC_CHIPID)));
117 change_cachability = (void (*)(uint32))KSEG1ADDR(_change_cachability);
125 uint32 start, end;
139 uint32 start, end;
155 uint32 control;
156 uint32 config;
157 uint32 cpupwrstatus;
158 uint32 invalidate;
159 uint32 rsvd1[4];
160 uint32 rsvd2[4];
161 uint32 rsvd3[4];
162 uint32 filtstart;
163 uint32 filtend;
164 uint32 rsvd4[2];
165 uint32 sac;
166 uint32 snsac;
170 uint32 cache_id;
171 uint32 cache_type;
172 uint32 rsvd1[62];
173 uint32 control; /* 0x100 */
174 uint32 aux_control;
175 uint32 tag_ram_control;
176 uint32 data_ram_control;
177 uint32 rsvd2[60];
178 uint32 ev_counter_ctrl; /* 0x200 */
179 uint32 ev_counter1_cfg;
180 uint32 ev_counter0_cfg;
181 uint32 ev_counter1;
182 uint32 ev_counter0;
183 uint32 int_mask;
184 uint32 int_mask_status;
185 uint32 int_raw_status;
186 uint32 int_clear;
187 uint32 rsvd3[55];
188 uint32 rsvd4[64]; /* 0x300 */
189 uint32 rsvd5[64]; /* 0x400 */
190 uint32 rsvd6[64]; /* 0x500 */
191 uint32 rsvd7[64]; /* 0x600 */
192 uint32 rsvd8[12]; /* 0x700 - 0x72F */
193 uint32 cache_sync; /* 0x730 */
194 uint32 rsvd9[15];
195 uint32 inv_pa; /* 0x770 */
196 uint32 rsvd10[2];
197 uint32 inv_way; /* 0x77C */
198 uint32 rsvd11[12];
199 uint32 clean_pa; /* 0x7B0 */
200 uint32 rsvd12[1];
201 uint32 clean_index; /* 0x7B8 */
202 uint32 clean_way;
203 uint32 rsvd13[12];
204 uint32 clean_inv_pa; /* 0x7F0 */
205 uint32 rsvd14[1];
206 uint32 clean_inv_index;
207 uint32 clean_inv_way;
208 uint32 rsvd15[64]; /* 0x800 - 0x8FF */
209 uint32 d_lockdown0; /* 0x900 */
210 uint32 i_lockdown0;
211 uint32 d_lockdown1;
212 uint32 i_lockdown1;
213 uint32 d_lockdown2;
214 uint32 i_lockdown2;
215 uint32 d_lockdown3;
216 uint32 i_lockdown3;
217 uint32 d_lockdown4;
218 uint32 i_lockdown4;
219 uint32 d_lockdown5;
220 uint32 i_lockdown5;
221 uint32 d_lockdown6;
222 uint32 i_lockdown6;
223 uint32 d_lockdown7;
224 uint32 i_lockdown7;
225 uint32 rsvd16[4]; /* 0x940 */
226 uint32 lock_line_en; /* 0x950 */
227 uint32 unlock_way;
228 uint32 rsvd17[42];
229 uint32 rsvd18[64]; /* 0xA00 */
230 uint32 rsvd19[64]; /* 0xB00 */
231 uint32 addr_filtering_start; /* 0xC00 */
232 uint32 addr_filtering_end;
233 uint32 rsvd20[62];
234 uint32 rsvd21[64]; /* 0xD00 */
235 uint32 rsvd22[64]; /* 0xE00 */
236 uint32 rsvd23[16]; /* 0xF00 - 0xF3F */
237 uint32 debug_ctrl; /* 0xF40 */
238 uint32 rsvd24[7];
239 uint32 prefetch_ctrl; /* 0xF60 */
240 uint32 rsvd25[7];
241 uint32 power_ctrl; /* 0xF80 */
304 uint32 regval;
369 uint32 val, *ptb, ptbaddr;
381 ptbaddr = (uint32)loader_pagetable_array;
385 ptb = (uint32 *)ptbaddr;
425 uint32 val;
449 uint32 val;
500 uint32 idx;
507 idx = *((uint32 *)OSL_UNCACHED((uintptr)&log_idx));
509 *((uint32 *)OSL_UNCACHED((uintptr)&log_idx)) = (idx + 1) & LOG_BUF_MASK;
591 #define get_arm_cyclecount (uint32)_getticks
595 uint32
604 static uint32 cpu_clock = 125000000;
605 static uint32 c0counts_per_us = 125000000 / 2000000;
606 static uint32 c0counts_per_ms = 125000000 / 2000;
609 udelay(uint32 us)
611 uint32 curr, lim;
675 uint32 c0counts_per_cycle;