Lines Matching refs:osh
68 static void si_pmu0_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal);
69 static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal);
70 static void si_pmu1_pllinit1(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal);
71 static void si_pmu2_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal);
72 static void si_pmu_pll_off(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 *min_mask,
74 static void si_pmu_pll_off_isdone(si_t *sih, osl_t *osh, chipcregs_t *cc);
75 static void si_pmu_pll_on(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 min_mask,
77 void si_pmu_otp_pllcontrol(si_t *sih, osl_t *osh);
78 void si_pmu_otp_regcontrol(si_t *sih, osl_t *osh);
79 void si_pmu_otp_chipcontrol(si_t *sih, osl_t *osh);
80 uint32 si_pmu_def_alp_clock(si_t *sih, osl_t *osh);
81 bool si_pmu_update_pllcontrol(si_t *sih, osl_t *osh, uint32 xtal, bool update_required);
84 static uint32 si_pmu0_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
85 static uint32 si_pmu0_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
86 static uint32 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
87 static uint32 si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
88 static uint32 si_pmu2_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
89 static uint32 si_pmu2_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
96 static uint32 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 rsrcs, bool all);
97 static uint si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc, uint8 rsrc);
99 static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh, uint8 spuravoid);
168 osl_t *osh;
174 osh = si_osh(sih);
180 si_pmu_pll_off(sih, osh, cc, &min_res_mask, &max_res_mask, &clk_ctl_st);
182 OR_REG(osh, &cc->pmucontrol, PCTL_PLL_PLLCTL_UPD);
183 si_pmu_pll_on(sih, osh, cc, min_res_mask, max_res_mask, clk_ctl_st);
194 BCMATTACHFN(si_pmu_otp_pllcontrol)(si_t *sih, osl_t *osh)
223 W_REG(osh, &cc->pllcontrol_addr, i);
224 W_REG(osh, &cc->pllcontrol_data, val);
235 BCMATTACHFN(si_pmu_otp_regcontrol)(si_t *sih, osl_t *osh)
264 W_REG(osh, &cc->regcontrol_addr, i);
265 W_REG(osh, &cc->regcontrol_data, val);
276 BCMATTACHFN(si_pmu_otp_chipcontrol)(si_t *sih, osl_t *osh)
302 W_REG(osh, &cc->chipcontrol_addr, i);
303 W_REG(osh, &cc->chipcontrol_data, val);
312 BCMATTACHFN(si_pmu_set_switcher_voltage)(si_t *sih, osl_t *osh,
325 W_REG(osh, &cc->regcontrol_addr, 0x01);
326 W_REG(osh, &cc->regcontrol_data, (uint32)(bb_voltage & 0x1f) << 22);
328 W_REG(osh, &cc->regcontrol_addr, 0x00);
329 W_REG(osh, &cc->regcontrol_data, (uint32)(rf_voltage & 0x1f) << 14);
341 BCMATTACHFN(si_pmu_set_ldo_voltage)(si_t *sih, osl_t *osh, uint8 ldo, uint8 voltage)
555 si_pmu_paref_ldo_enable(si_t *sih, osl_t *osh, bool enable)
588 BCMINITFN(si_pmu_fast_pwrup_delay)(si_t *sih, osl_t *osh)
637 pmudelay = (si_pmu_res_uptime(sih, osh, cc, RES4325_HT_AVAIL) +
647 pmudelay = (si_pmu_res_uptime(sih, osh, cc, RES4329_HT_AVAIL) +
657 pmudelay = (si_pmu_res_uptime(sih, osh, cc, RES4315_HT_AVAIL) +
671 pmudelay = (si_pmu_res_uptime(sih, osh, cc, RES4336_HT_AVAIL) +
681 pmudelay = (si_pmu_res_uptime(sih, osh, cc, RES4330_HT_AVAIL) +
693 pmudelay = (si_pmu_res_uptime(sih, osh, cc, RES4314_HT_AVAIL) +
704 pmudelay = (si_pmu_res_uptime(sih, osh, cc, RES43143_HT_AVAIL) +
715 pmudelay = (si_pmu_res_uptime(sih, osh, cc, RES4334_HT_AVAIL) +
725 pmudelay = (si_pmu_res_uptime(sih, osh, cc, RES4335_HT_AVAIL) +
736 pmudelay = (si_pmu_res_uptime(sih, osh, cc, RES4350_HT_AVAIL) +
749 pmudelay = (si_pmu_res_uptime(sih, osh, cc, RES4324_HT_AVAIL) +
765 BCMATTACHFN(si_pmu_force_ilp)(si_t *sih, osl_t *osh, bool force)
778 oldpmucontrol = R_REG(osh, &cc->pmucontrol);
780 W_REG(osh, &cc->pmucontrol, oldpmucontrol &
783 W_REG(osh, &cc->pmucontrol, oldpmucontrol |
793 BCMATTACHFN(si_pmu_enb_ht_req)(si_t *sih, osl_t *osh, bool enb)
806 oldpmucontrol = R_REG(osh, &cc->pmucontrol);
808 W_REG(osh, &cc->pmucontrol, oldpmucontrol | PCTL_HT_REQ_EN);
810 W_REG(osh, &cc->pmucontrol, oldpmucontrol & ~PCTL_HT_REQ_EN);
2176 BCMATTACHFN(si_pmu_res_init)(si_t *sih, osl_t *osh)
2312 W_REG(osh, &cc->chipcontrol_addr, PMU_CHIPCTL3);
2313 tmp = R_REG(osh, &cc->chipcontrol_data);
2315 W_REG(osh, &cc->chipcontrol_data, tmp);
2388 W_REG(osh, &cc->res_table_sel,
2390 W_REG(osh, &cc->res_updn_timer,
2409 W_REG(osh, &cc->res_table_sel, (uint32)i);
2410 W_REG(osh, &cc->res_updn_timer, r_val);
2423 W_REG(osh, &cc->res_table_sel, i);
2428 W_REG(osh, &cc->res_dep_mask,
2434 OR_REG(osh, &cc->res_dep_mask,
2440 AND_REG(osh, &cc->res_dep_mask,
2455 W_REG(osh, &cc->res_table_sel, (uint32)i);
2456 W_REG(osh, &cc->res_dep_mask, (uint32)bcm_strtoul(val, NULL, 0));
2463 min_mask |= si_pmu_res_deps(sih, osh, cc, min_mask, FALSE);
2468 min_mask |= R_REG(osh, &cc->min_res_mask);
2469 max_mask |= R_REG(osh, &cc->max_res_mask);
2492 W_REG(osh, &cc->pllcontrol_addr, 6);
2493 W_REG(osh, &cc->pllcontrol_data, 0x09048560);
2495 W_REG(osh, &cc->pllcontrol_addr, 14);
2496 W_REG(osh, &cc->pllcontrol_data, 0x09048560);
2511 OR_REG(osh, &cc->max_res_mask, max_mask);
2520 OR_REG(osh, &cc->max_res_mask, min_mask);
2526 W_REG(osh, &cc->min_res_mask, min_mask);
2532 W_REG(osh, &cc->max_res_mask, max_mask);
2592 W_REG(osh, &cc->pllcontrol_addr, PMU0_PLL0_PLLCTL0);
2593 tmp = R_REG(osh, &cc->pllcontrol_data);
2596 W_REG(osh, &cc->pllcontrol_data, tmp);
2600 oldmin = R_REG(osh, &cc->min_res_mask);
2601 oldmax = R_REG(osh, &cc->max_res_mask);
2602 W_REG(osh, &cc->min_res_mask, oldmin & ~PMURES_BIT(RES4328_BB_PLL_PU));
2603 W_REG(osh, &cc->max_res_mask, oldmax & ~PMURES_BIT(RES4328_BB_PLL_PU));
2612 SPINWAIT((R_REG(osh, &cc->res_state) & PMURES_BIT(RES4328_BB_PLL_PU)), PLL_DELAY*3);
2613 if (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4328_BB_PLL_PU)) {
2620 ASSERT(!(R_REG(osh, &cc->res_state) & PMURES_BIT(RES4328_BB_PLL_PU)));
2624 W_REG(osh, &cc->max_res_mask, oldmax);
2636 BCMATTACHFN(si_pmu0_pllinit0)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal)
2651 tmp = (R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
2675 AND_REG(osh, &cc->min_res_mask, ~PMURES_BIT(RES4328_BB_PLL_PU));
2676 AND_REG(osh, &cc->max_res_mask, ~PMURES_BIT(RES4328_BB_PLL_PU));
2679 AND_REG(osh, &cc->min_res_mask, ~PMURES_BIT(RES5354_BB_PLL_PU));
2680 AND_REG(osh, &cc->max_res_mask, ~PMURES_BIT(RES5354_BB_PLL_PU));
2685 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS0_HTAVAIL, PMU_MAX_TRANSITION_DLY);
2686 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS0_HTAVAIL));
2691 W_REG(osh, &cc->pllcontrol_addr, PMU0_PLL0_PLLCTL0);
2692 tmp = R_REG(osh, &cc->pllcontrol_data);
2697 W_REG(osh, &cc->pllcontrol_data, tmp);
2700 W_REG(osh, &cc->pllcontrol_addr, PMU0_PLL0_PLLCTL1);
2701 tmp = R_REG(osh, &cc->pllcontrol_data);
2711 W_REG(osh, &cc->pllcontrol_data, tmp);
2714 W_REG(osh, &cc->pllcontrol_addr, PMU0_PLL0_PLLCTL2);
2715 tmp = R_REG(osh, &cc->pllcontrol_data);
2719 W_REG(osh, &cc->pllcontrol_data, tmp);
2724 tmp = R_REG(osh, &cc->pmucontrol);
2729 W_REG(osh, &cc->pmucontrol, tmp);
2734 BCMINITFN(si_pmu0_alpclk0)(si_t *sih, osl_t *osh, chipcregs_t *cc)
2740 xf = (R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
2753 BCMINITFN(si_pmu0_cpuclk0)(si_t *sih, osl_t *osh, chipcregs_t *cc)
2759 W_REG(osh, &cc->pllcontrol_addr, PMU0_PLL0_PLLCTL0);
2760 tmp = R_REG(osh, &cc->pllcontrol_data);
3292 osl_t *osh;
3293 osh = si_osh(sih);
3319 return (si_pmu_cal_fvco(sih, osh));
3335 BCMINITFN(si_pmu1_alpclk0)(si_t *sih, osl_t *osh, chipcregs_t *cc)
3341 xf = (R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
3411 si_pmu_minresmask_htavail_set(si_t *sih, osl_t *osh, bool set_clear)
3424 AND_REG(osh, &cc->min_res_mask,
3437 si_pll_minresmask_reset(si_t *sih, osl_t *osh)
3451 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4313_HT_AVAIL_RSRC)));
3454 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4313_HT_AVAIL_RSRC)));
3457 OR_REG(osh, &cc->max_res_mask, (PMURES_BIT(RES4313_HT_AVAIL_RSRC)));
3470 BCMATTACHFN(si_pmu_def_alp_clock)(si_t *sih, osl_t *osh)
3498 BCMATTACHFN(si_pmu_pllctrlreg_update)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal,
3525 W_REG(osh, &cc->pllcontrol_addr, reg_offset);
3526 W_REG(osh, &cc->pllcontrol_data,
3548 BCMATTACHFN(si_pmu_update_pllcontrol)(si_t *sih, osl_t *osh, uint32 xtal, bool update_required)
3575 if (xtal != (si_pmu_def_alp_clock(sih, osh)/1000))
3582 xtal = si_pmu_def_alp_clock(sih, osh)/1000;
3681 xf = si_pmu_pllctrlreg_update(sih, osh, NULL, xtal, 0, pllctrlreg_update,
3687 tmp = R_REG(osh, &cc->pmucontrol) &
3692 W_REG(osh, &cc->pmucontrol, tmp);
3706 si_pmu_pllctrlreg_update(sih, osh, cc, xtal, 0, pllctrlreg_update, array_size,
3746 int si_pmu_wait_for_steady_state(osl_t *osh, chipcregs_t *cc);
3749 si_pmu_get_pmutime_diff(osl_t *osh, chipcregs_t *cc, uint32 *prev);
3752 si_pmu_wait_for_res_pending(osl_t *osh, chipcregs_t *cc, uint usec,
3756 si_pmu_get_pmutimer(osl_t *osh, chipcregs_t *cc);
3762 si_pmu_get_pmutimer(osl_t *osh, chipcregs_t *cc)
3765 start = R_REG(osh, &cc->pmutimer);
3766 if (start != R_REG(osh, &cc->pmutimer))
3767 start = R_REG(osh, &cc->pmutimer);
3777 si_pmu_get_pmutime_diff(osl_t *osh, chipcregs_t *cc, uint32 *prev)
3783 pmutime_val = si_pmu_get_pmutimer(osh, cc);
3801 si_pmu_wait_for_res_pending(osl_t *osh, chipcregs_t *cc, uint usec,
3810 pmutime_prev = si_pmu_get_pmutimer(osh, cc);
3812 res_pend = R_REG(osh, &cc->res_pending);
3831 pmutime_elapsed += si_pmu_get_pmutime_diff(osh, cc, &pmutime_prev);
3851 int si_pmu_wait_for_steady_state(osl_t *osh, chipcregs_t *cc)
3859 timedout = si_pmu_wait_for_res_pending(osh, cc,
3874 timedout = si_pmu_wait_for_res_pending(osh, cc,
3900 si_pmu_pll_off(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 *min_mask,
3906 *min_mask = R_REG(osh, &cc->min_res_mask);
3907 *max_mask = R_REG(osh, &cc->max_res_mask);
3908 *clk_ctl_st = R_REG(osh, &cc->clk_ctl_st);
3919 if (((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) != CCS_HTAVAIL))
3920 si_pmu_wait_for_steady_state(osh, cc);
3922 OR_REG(osh, &cc->max_res_mask, ht_req);
3924 SPINWAIT(((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) != CCS_HTAVAIL),
3926 ASSERT((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
3929 AND_REG(osh, &cc->min_res_mask, ~ht_req);
3930 AND_REG(osh, &cc->max_res_mask, ~ht_req);
3932 SPINWAIT(((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) == CCS_HTAVAIL),
3934 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
3942 si_pmu_pll_off_PARR(si_t *sih, osl_t *osh, uint32 *min_mask,
3954 *min_mask = R_REG(osh, &cc->min_res_mask);
3955 *max_mask = R_REG(osh, &cc->max_res_mask);
3956 *clk_ctl_st = R_REG(osh, &cc->clk_ctl_st);
3967 if (((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) != CCS_HTAVAIL))
3968 si_pmu_wait_for_steady_state(osh, cc);
3970 OR_REG(osh, &cc->max_res_mask, ht_req);
3972 SPINWAIT(((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) != CCS_HTAVAIL),
3974 ASSERT((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
3977 AND_REG(osh, &cc->min_res_mask, ~ht_req);
3978 AND_REG(osh, &cc->max_res_mask, ~ht_req);
3986 si_pmu_pll_off_isdone(si_t *sih, osl_t *osh, chipcregs_t *cc)
3990 SPINWAIT(((R_REG(osh, &cc->res_state) & ht_req) != 0),
3992 SPINWAIT(((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) == CCS_HTAVAIL),
3994 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
4002 si_pmu_pll_on(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 min_mask_mask,
4015 OR_REG(osh, &cc->max_res_mask, max_mask_mask);
4018 OR_REG(osh, &cc->min_res_mask, min_mask_mask);
4022 SPINWAIT(((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) != CCS_HTAVAIL),
4024 ASSERT((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
4095 BCMATTACHFN(si_pmu2_pll_vars_init)(si_t *sih, osl_t *osh, chipcregs_t *cc)
4128 si_pmu_pll_off(sih, osh, cc, &min_mask, &max_mask, &clk_ctl_st);
4131 si_pmu_otp_pllcontrol(sih, osh);
4135 OR_REG(osh, &cc->pmucontrol, PCTL_PLL_PLLCTL_UPD);
4140 si_pmu_pll_on(sih, osh, cc, min_mask, max_mask, clk_ctl_st);
4148 BCMATTACHFN(si_pmu2_pllinit0)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal)
4170 W_REG(osh, &cc->pllcontrol_addr, PMU15_PLL_PLLCTL0);
4171 pll0 = R_REG(osh, &cc->pllcontrol_data);
4186 AND_REG(osh, &cc->min_res_mask,
4188 AND_REG(osh, &cc->max_res_mask,
4190 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, PMU_MAX_TRANSITION_DLY);
4191 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
4195 AND_REG(osh, &cc->min_res_mask,
4197 AND_REG(osh, &cc->max_res_mask,
4199 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, PMU_MAX_TRANSITION_DLY);
4200 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
4203 AND_REG(osh, &cc->min_res_mask,
4205 AND_REG(osh, &cc->max_res_mask,
4207 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, PMU_MAX_TRANSITION_DLY);
4208 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
4216 W_REG(osh, &cc->pllcontrol_data, pll0);
4234 OR_REG(osh, &cc->pmucontrol, PCTL_PLL_PLLCTL_UPD);
4238 si_pmu2_pll_vars_init(sih, osh, cc);
4243 BCMINITFN(si_pmu2_cpuclk0)(si_t *sih, osl_t *osh, chipcregs_t *cc)
4253 W_REG(osh, &cc->pllcontrol_addr, PMU15_PLL_PLLCTL0);
4254 pll0 = R_REG(osh, &cc->pllcontrol_data);
4280 BCMINITFN(si_pmu2_alpclk0)(si_t *sih, osl_t *osh, chipcregs_t *cc)
4285 W_REG(osh, &cc->pllcontrol_addr, PMU15_PLL_PLLCTL0);
4286 pll0 = R_REG(osh, &cc->pllcontrol_data);
4315 BCMATTACHFN(si_pmu1_pllinit1)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal)
4343 pll_reg_update_required = si_pmu_update_pllcontrol(sih, osh, xtal, FALSE);
4350 si_pmu_pll_off(sih, osh, cc, &min_mask, &max_mask, &clk_ctl_st);
4354 si_pmu_update_pllcontrol(sih, osh, xtal, TRUE);
4358 si_pmu_otp_pllcontrol(sih, osh);
4362 OR_REG(osh, &cc->pmucontrol, PCTL_PLL_PLLCTL_UPD);
4367 si_pmu_pll_on(sih, osh, cc, min_mask, max_mask, clk_ctl_st);
4378 BCMATTACHFN(si_pmu1_pllinit0)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal)
4408 if ((((R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
4425 AND_REG(osh, &cc->min_res_mask,
4427 AND_REG(osh, &cc->max_res_mask,
4429 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, PMU_MAX_TRANSITION_DLY);
4430 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
4435 AND_REG(osh, &cc->min_res_mask,
4437 AND_REG(osh, &cc->max_res_mask,
4439 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, PMU_MAX_TRANSITION_DLY);
4440 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
4441 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
4450 W_REG(osh, &cc->pllcontrol_data, tmp);
4451 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
4452 tmp = R_REG(osh, &cc->pllcontrol_data) & PMU1_PLL0_PC5_CLK_DRV_MASK;
4457 W_REG(osh, &cc->pllcontrol_data, tmp);
4463 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4315_HT_AVAIL)));
4464 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4315_HT_AVAIL)));
4467 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4315_BBPLL_PWRSW_PU)));
4468 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4315_BBPLL_PWRSW_PU)));
4471 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, PMU_MAX_TRANSITION_DLY);
4472 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
4484 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4319_HT_AVAIL)));
4485 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4319_HT_AVAIL)));
4488 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
4489 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
4492 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, PMU_MAX_TRANSITION_DLY);
4493 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
4494 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
4496 W_REG(osh, &cc->pllcontrol_data, tmp);
4501 AND_REG(osh, &cc->min_res_mask,
4503 AND_REG(osh, &cc->max_res_mask,
4506 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, PMU_MAX_TRANSITION_DLY);
4507 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
4511 AND_REG(osh, &cc->min_res_mask,
4513 AND_REG(osh, &cc->max_res_mask,
4516 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, PMU_MAX_TRANSITION_DLY);
4517 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
4527 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
4528 tmp = R_REG(osh, &cc->pllcontrol_data) &
4532 W_REG(osh, &cc->pllcontrol_data, tmp);
4546 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
4547 tmp = R_REG(osh, &cc->pllcontrol_data);
4550 W_REG(osh, &cc->pllcontrol_data, tmp);
4561 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
4562 tmp = R_REG(osh, &cc->pllcontrol_data) &
4566 W_REG(osh, &cc->pllcontrol_data, tmp);
4569 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
4570 tmp = R_REG(osh, &cc->pllcontrol_data) & ~PMU1_PLL0_PC3_NDIV_FRAC_MASK;
4573 W_REG(osh, &cc->pllcontrol_data, tmp);
4579 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
4580 tmp = R_REG(osh, &cc->pllcontrol_data) & ~PMU1_PLL0_PC5_CLK_DRV_MASK;
4582 W_REG(osh, &cc->pllcontrol_data, tmp);
4591 W_REG(osh, &cc->chipcontrol_addr, PMU1_PLL0_CHIPCTL2);
4592 tmp = R_REG(osh, &cc->chipcontrol_data) & ~CCTL_4319USB_XTAL_SEL_MASK;
4598 W_REG(osh, &cc->chipcontrol_data, tmp);
4603 OR_REG(osh, &cc->pmucontrol, PCTL_PLL_PLLCTL_UPD);
4606 tmp = R_REG(osh, &cc->pmucontrol) &
4614 AND_REG(osh, &cc->clkstretch, ~CSTRETCH_HT);
4618 W_REG(osh, &cc->pmucontrol, tmp);
4626 BCMINITFN(si_pmu1_cpuclk0)(si_t *sih, osl_t *osh, chipcregs_t *cc)
4642 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
4643 tmp = R_REG(osh, &cc->pllcontrol_data);
4648 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
4649 tmp = R_REG(osh, &cc->pllcontrol_data);
4656 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
4657 tmp = R_REG(osh, &cc->pllcontrol_data);
4663 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
4664 tmp = R_REG(osh, &cc->pllcontrol_data);
4672 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
4673 tmp = R_REG(osh, &cc->pllcontrol_data);
4689 si_mac_clk(si_t *sih, osl_t *osh)
4724 si_pmu_is_autoresetphyclk_disabled(si_t *sih, osl_t *osh)
4737 W_REG(osh, &cc->chipcontrol_addr, 0);
4738 if (R_REG(osh, &cc->chipcontrol_data) & 0x00000002)
4751 BCMATTACHFN(si_set_bb_vcofreq_frac)(si_t *sih, osl_t *osh, int vcofreq, int frac, int xtalfreq)
4765 if (R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL) {
4815 si_pmu_get_bb_vcofreq(si_t *sih, osl_t *osh, int xtalfreq)
4873 BCMATTACHFN(si_pmu_pll_init)(si_t *sih, osl_t *osh, uint xtalfreq)
4887 si_pmu0_pllinit0(sih, osh, cc, xtalfreq);
4892 si_pmu0_pllinit0(sih, osh, cc, xtalfreq);
4895 si_pmu1_pllinit0(sih, osh, cc, xtalfreq);
4900 si_pmu1_pllinit0(sih, osh, cc, xtalfreq);
4912 minmask = R_REG(osh, &cc->min_res_mask);
4913 maxmask = R_REG(osh, &cc->max_res_mask);
4917 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4322_HT_SI_AVAIL)));
4918 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4322_HT_SI_AVAIL)));
4919 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, PMU_MAX_TRANSITION_DLY);
4920 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4322_SI_PLL_ON)));
4921 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4322_SI_PLL_ON)));
4923 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
4926 W_REG(osh, &cc->pllcontrol_addr, PMU2_SI_PLL_PLLCTL);
4927 W_REG(osh, &cc->pllcontrol_data, 0x380005c0);
4931 W_REG(osh, &cc->max_res_mask, maxmask);
4933 W_REG(osh, &cc->min_res_mask, minmask);
4944 si_set_bb_vcofreq_frac(sih, osh, 960, 98, 40);
4971 si_pmu1_pllinit0(sih, osh, cc, xtalfreq);
4978 si_pmu1_pllinit1(sih, osh, cc, xtalfreq);
4981 si_pmu1_pllinit1(sih, osh, cc, xtalfreq);
4983 si_set_bb_vcofreq_frac(sih, osh, 968, 0, 40);
4990 si_pmu2_pllinit0(sih, osh, cc, xtalfreq);
4993 si_pmu2_pllinit0(sih, osh, cc, xtalfreq);
5002 OR_REG(osh, &cc->clk_ctl_st, CCS_FORCEHT);
5011 BCMINITFN(si_pmu_alp_clock)(si_t *sih, osl_t *osh)
5026 clock = si_pmu0_alpclk0(sih, osh, cc);
5029 clock = si_pmu0_alpclk0(sih, osh, cc);
5032 clock = si_pmu1_alpclk0(sih, osh, cc);
5084 clock = si_pmu1_alpclk0(sih, osh, cc);
5090 clock = si_pmu2_alpclk0(sih, osh, cc);
5114 BCMINITFN(si_pmu5_clock)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0, uint m)
5133 if ((R_REG(osh, &cc->chipstatus) & 0x40000) != 0) {
5138 W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_P1P2_OFF);
5139 (void)R_REG(osh, &cc->pllcontrol_addr);
5140 tmp = R_REG(osh, &cc->pllcontrol_data);
5144 W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_M14_OFF);
5145 (void)R_REG(osh, &cc->pllcontrol_addr);
5146 tmp = R_REG(osh, &cc->pllcontrol_data);
5149 W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU5_PLL_NM5_OFF);
5150 (void)R_REG(osh, &cc->pllcontrol_addr);
5151 tmp = R_REG(osh, &cc->pllcontrol_data);
5155 fc = si_pmu_alp_clock(sih, osh) / 1000000;
5166 BCMINITFN(si_4706_pmu_clock)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0, uint m)
5178 W_REG(osh, &cc->pllcontrol_addr, pll0 + PMU6_4706_PROCPLL_OFF);
5184 if (R_REG(osh, &cc->chipstatus) & CST4706_PKG_OPTION)
5205 BCMINITFN(si_pmu_si_clock)(si_t *sih, osl_t *osh)
5220 clock = si_pmu0_cpuclk0(sih, osh, cc);
5226 clock = si_pmu1_cpuclk0(sih, osh, cc);
5245 clock = si_pmu5_clock(sih, osh, cc, PMU4716_MAINPLL_PLL0, PMU5_MAINPLL_SI);
5251 clock = si_pmu1_cpuclk0(sih, osh, cc);
5268 clock = si_pmu1_cpuclk0(sih, osh, cc);
5279 clock = si_pmu2_cpuclk0(sih, osh, cc);
5287 clock = si_pmu5_clock(sih, osh, cc, PMU5356_MAINPLL_PLL0, PMU5_MAINPLL_SI);
5291 clock = si_pmu5_clock(sih, osh, cc, PMU5357_MAINPLL_PLL0, PMU5_MAINPLL_SI);
5297 clock = si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_SI);
5313 BCMINITFN(si_pmu_cpu_clock)(si_t *sih, osl_t *osh)
5375 clock = si_4706_pmu_clock(sih, osh, cc,
5378 clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_CPU);
5383 clock = si_pmu_si_clock(sih, osh);
5390 BCMINITFN(si_pmu_mem_clock)(si_t *sih, osl_t *osh)
5444 clock = si_4706_pmu_clock(sih, osh, cc,
5447 clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_MEM);
5452 clock = si_pmu_si_clock(sih, osh);
5464 BCMINITFN(si_pmu_ilp_clock)(si_t *sih, osl_t *osh)
5474 start = R_REG(osh, &cc->pmutimer);
5475 if (start != R_REG(osh, &cc->pmutimer))
5476 start = R_REG(osh, &cc->pmutimer);
5478 end = R_REG(osh, &cc->pmutimer);
5479 if (end != R_REG(osh, &cc->pmutimer))
5480 end = R_REG(osh, &cc->pmutimer);
5565 BCMINITFN(si_sdiod_drive_strength_init)(si_t *sih, osl_t *osh, uint32 drivestrength)
5634 W_REG(osh, &cc->chipcontrol_addr, 1);
5635 cc_data_temp = R_REG(osh, &cc->chipcontrol_data);
5638 W_REG(osh, &cc->chipcontrol_data, cc_data_temp);
5650 BCMATTACHFN(si_pmu_init)(si_t *sih, osl_t *osh)
5663 AND_REG(osh, &cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
5665 OR_REG(osh, &cc->pmucontrol, PCTL_NOILP_ON_WAIT);
5669 W_REG(osh, &cc->regcontrol_addr, 2);
5670 OR_REG(osh, &cc->regcontrol_data, 0x100);
5672 W_REG(osh, &cc->regcontrol_addr, 3);
5673 OR_REG(osh, &cc->regcontrol_data, 0x4);
5699 BCMINITFN(si_pmu_res_uptime)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint8 rsrc)
5706 W_REG(osh, &cc->res_table_sel, rsrc);
5708 uptime = (R_REG(osh, &cc->res_updn_timer) >> 16) & 0x3ff;
5710 uptime = (R_REG(osh, &cc->res_updn_timer) >> 8) & 0xff;
5713 deps = si_pmu_res_deps(sih, osh, cc, PMURES_BIT(rsrc), FALSE);
5717 deps &= ~si_pmu_res_deps(sih, osh, cc, PMURES_BIT(i), TRUE);
5727 dup = si_pmu_res_uptime(sih, osh, cc, (uint8)i);
5740 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 rsrcs, bool all)
5748 W_REG(osh, &cc->res_table_sel, i);
5749 deps |= R_REG(osh, &cc->res_dep_mask);
5752 return !all ? deps : (deps ? (deps | si_pmu_res_deps(sih, osh, cc, deps, TRUE)) : 0);
5760 si_pmu_otp_power(si_t *sih, osl_t *osh, bool on)
5840 uint32 deps = si_pmu_res_deps(sih, osh, cc, rsrcs, TRUE);
5847 OR_REG(osh, &cc->min_res_mask, (rsrcs | deps));
5849 SPINWAIT(!(R_REG(osh, &cc->res_state) & rsrcs), PMU_MAX_TRANSITION_DLY);
5850 ASSERT(R_REG(osh, &cc->res_state) & rsrcs);
5854 AND_REG(osh, &cc->min_res_mask, ~(rsrcs | deps));
5857 SPINWAIT((((otps = R_REG(osh, &cc->otpstatus)) & OTPS_READY) !=
5870 si_pmu_rcal(si_t *sih, osl_t *osh)
5889 W_REG(osh, &cc->chipcontrol_addr, 1);
5892 AND_REG(osh, &cc->chipcontrol_data, ~0x04);
5895 rcal_done = ((R_REG(osh, &cc->chipstatus)) & 0x8) >> 3;
5905 OR_REG(osh, &cc->chipcontrol_data, 0x04);
5908 SPINWAIT(!(R_REG(osh, &cc->chipstatus) & 0x08), 10 * 1000 * 1000);
5909 ASSERT(R_REG(osh, &cc->chipstatus) & 0x08);
5915 rcal_code = (uint8)(R_REG(osh, &cc->chipstatus) >> 5) & 0x0f;
5919 R_REG(osh, &cc->chipstatus), rcal_code));
5922 W_REG(osh, &cc->regcontrol_addr, 0);
5923 val = R_REG(osh, &cc->regcontrol_data) & ~((uint32)0x07 << 29);
5925 W_REG(osh, &cc->regcontrol_data, val);
5926 W_REG(osh, &cc->regcontrol_addr, 1);
5927 val = R_REG(osh, &cc->regcontrol_data) & ~(uint32)0x01;
5929 W_REG(osh, &cc->regcontrol_data, val);
5932 W_REG(osh, &cc->chipcontrol_addr, 0);
5933 val = R_REG(osh, &cc->chipcontrol_data) & ~((uint32)0x03 << 30);
5935 W_REG(osh, &cc->chipcontrol_data, val);
5936 W_REG(osh, &cc->chipcontrol_addr, 1);
5937 val = R_REG(osh, &cc->chipcontrol_data) & ~(uint32)0x03;
5939 W_REG(osh, &cc->chipcontrol_data, val);
5942 W_REG(osh, &cc->chipcontrol_addr, 0);
5943 OR_REG(osh, &cc->chipcontrol_data, (0x01 << 29));
5946 W_REG(osh, &cc->chipcontrol_addr, 1);
5947 AND_REG(osh, &cc->chipcontrol_data, ~0x04);
5956 W_REG(osh, &cc->chipcontrol_addr, 1);
5959 AND_REG(osh, &cc->chipcontrol_data, ~0x04);
5962 OR_REG(osh, &cc->chipcontrol_data, 0x04);
5965 SPINWAIT(!(R_REG(osh, &cc->chipstatus) & 0x08), 10 * 1000 * 1000);
5966 ASSERT(R_REG(osh, &cc->chipstatus) & 0x08);
5969 rcal_code = (uint8)(R_REG(osh, &cc->chipstatus) >> 5) & 0x0f;
5972 R_REG(osh, &cc->chipstatus), rcal_code));
5975 W_REG(osh, &cc->regcontrol_addr, 0);
5976 val = R_REG(osh, &cc->regcontrol_data) & ~((uint32)0x07 << 29);
5978 W_REG(osh, &cc->regcontrol_data, val);
5979 W_REG(osh, &cc->regcontrol_addr, 1);
5980 val = R_REG(osh, &cc->regcontrol_data) & ~(uint32)0x01;
5982 W_REG(osh, &cc->regcontrol_data, val);
5985 W_REG(osh, &cc->chipcontrol_addr, 0);
5986 val = R_REG(osh, &cc->chipcontrol_data) & ~((uint32)0x03 << 30);
5988 W_REG(osh, &cc->chipcontrol_data, val);
5989 W_REG(osh, &cc->chipcontrol_addr, 1);
5990 val = R_REG(osh, &cc->chipcontrol_data) & ~(uint32)0x03;
5992 W_REG(osh, &cc->chipcontrol_data, val);
5995 W_REG(osh, &cc->chipcontrol_addr, 0);
5996 OR_REG(osh, &cc->chipcontrol_data, (0x01 << 29));
5999 W_REG(osh, &cc->chipcontrol_addr, 1);
6000 AND_REG(osh, &cc->chipcontrol_data, ~0x04);
6014 si_pmu_spuravoid(si_t *sih, osl_t *osh, uint8 spuravoid)
6053 si_pmu_pll_off(sih, osh, cc, &min_res_mask, &max_res_mask, &clk_ctl_st);
6056 si_pmu_spuravoid_pllupdate(sih, cc, osh, spuravoid);
6060 si_pmu_pll_on(sih, osh, cc, min_res_mask, max_res_mask, clk_ctl_st);
6069 si_pmu_spuravoid_isdone(si_t *sih, osl_t *osh, uint32 min_res_mask,
6107 si_pmu_pll_off_isdone(sih, osh, cc);
6109 si_pmu_spuravoid_pllupdate(sih, cc, osh, spuravoid);
6113 si_pmu_pll_on(sih, osh, cc, min_res_mask, max_res_mask, clk_ctl_st);
6154 si_pmu_pllctrl_spurupdate(osl_t *osh, chipcregs_t *cc, uint8 spuravoid,
6160 W_REG(osh, &cc->pllcontrol_addr, pllctrl_spur[indx].pllctrl_reg);
6161 W_REG(osh, &cc->pllcontrol_data, pllctrl_spur[indx].pllctrl_regval);
6167 si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh, uint8 spuravoid)
6182 si_pmu_pllctrl_spurupdate(osh, cc, spuravoid, spuravoid_4324,
6198 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6199 W_REG(osh, &cc->pllcontrol_data, 0x11500010);
6200 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
6201 W_REG(osh, &cc->pllcontrol_data, 0x000C0C06);
6202 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6203 W_REG(osh, &cc->pllcontrol_data, 0x0F600a08);
6204 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6205 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
6206 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
6207 W_REG(osh, &cc->pllcontrol_data, 0x2001E920);
6208 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
6209 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
6211 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6212 W_REG(osh, &cc->pllcontrol_data, 0x11100010);
6213 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
6214 W_REG(osh, &cc->pllcontrol_data, 0x000c0c06);
6215 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6216 W_REG(osh, &cc->pllcontrol_data, 0x03000a08);
6217 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6218 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
6219 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
6220 W_REG(osh, &cc->pllcontrol_data, 0x200005c0);
6221 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
6222 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
6239 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0 + phypll_offset);
6240 tmp = R_REG(osh, &cc->pllcontrol_data);
6243 W_REG(osh, &cc->pllcontrol_data, tmp);
6246 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2 + phypll_offset);
6247 tmp = R_REG(osh, &cc->pllcontrol_data);
6250 W_REG(osh, &cc->pllcontrol_data, tmp);
6260 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6261 W_REG(osh, &cc->pllcontrol_data, 0x00000002);
6263 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6264 W_REG(osh, &cc->pllcontrol_data, 0x00000001);
6266 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6267 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
6271 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6272 W_REG(osh, &cc->pllcontrol_data, 0x11500014);
6273 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6274 W_REG(osh, &cc->pllcontrol_data, 0x0FC00a08);
6276 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6277 W_REG(osh, &cc->pllcontrol_data, 0x11500014);
6278 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6279 W_REG(osh, &cc->pllcontrol_data, 0x0F600a08);
6281 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6282 W_REG(osh, &cc->pllcontrol_data, 0x11100014);
6283 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6284 W_REG(osh, &cc->pllcontrol_data, 0x03000a08);
6293 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6294 W_REG(osh, &cc->pllcontrol_data, 0x11500010);
6295 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
6296 W_REG(osh, &cc->pllcontrol_data, 0x000C0C06);
6297 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6298 W_REG(osh, &cc->pllcontrol_data, 0x0F600a08);
6299 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6300 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
6301 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
6302 W_REG(osh, &cc->pllcontrol_data, 0x2001E920);
6303 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
6304 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
6306 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6307 W_REG(osh, &cc->pllcontrol_data, 0x11100010);
6308 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
6309 W_REG(osh, &cc->pllcontrol_data, 0x000c0c06);
6310 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6311 W_REG(osh, &cc->pllcontrol_data, 0x03000a08);
6312 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6313 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
6314 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
6315 W_REG(osh, &cc->pllcontrol_data, 0x200005c0);
6316 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
6317 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
6325 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6326 W_REG(osh, &cc->pllcontrol_data, 0x11500008);
6327 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
6328 W_REG(osh, &cc->pllcontrol_data, 0x0C000C06);
6329 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6330 W_REG(osh, &cc->pllcontrol_data, 0x0F600a08);
6331 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6332 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
6333 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
6334 W_REG(osh, &cc->pllcontrol_data, 0x2001E920);
6335 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
6336 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
6338 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6339 W_REG(osh, &cc->pllcontrol_data, 0x11100008);
6340 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
6341 W_REG(osh, &cc->pllcontrol_data, 0x0c000c06);
6342 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6343 W_REG(osh, &cc->pllcontrol_data, 0x03000a08);
6344 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6345 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
6346 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
6347 W_REG(osh, &cc->pllcontrol_data, 0x200005c0);
6348 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
6349 W_REG(osh, &cc->pllcontrol_data, 0x88888855);
6359 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6360 W_REG(osh, &cc->pllcontrol_data, 0x11500060);
6361 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
6362 W_REG(osh, &cc->pllcontrol_data, 0x080C0C06);
6363 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6364 W_REG(osh, &cc->pllcontrol_data, 0x0F600000);
6365 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6366 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
6367 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
6368 W_REG(osh, &cc->pllcontrol_data, 0x2001E924);
6369 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
6370 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
6372 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6373 W_REG(osh, &cc->pllcontrol_data, 0x11100060);
6374 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
6375 W_REG(osh, &cc->pllcontrol_data, 0x080c0c06);
6376 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6377 W_REG(osh, &cc->pllcontrol_data, 0x03000000);
6378 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6379 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
6380 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
6381 W_REG(osh, &cc->pllcontrol_data, 0x200005c0);
6382 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
6383 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
6393 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6394 W_REG(osh, &cc->pllcontrol_data, 0x11100070);
6395 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
6396 W_REG(osh, &cc->pllcontrol_data, 0x1014140a);
6397 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
6398 W_REG(osh, &cc->pllcontrol_data, 0x88888854);
6401 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6402 W_REG(osh, &cc->pllcontrol_data, 0x05201828);
6404 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6405 W_REG(osh, &cc->pllcontrol_data, 0x05001828);
6411 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6412 W_REG(osh, &cc->pllcontrol_data, 0x11100070);
6413 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
6414 W_REG(osh, &cc->pllcontrol_data, 0x1014140a);
6415 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
6416 W_REG(osh, &cc->pllcontrol_data, 0x88888854);
6419 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6420 W_REG(osh, &cc->pllcontrol_data, 0x05201828);
6422 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6423 W_REG(osh, &cc->pllcontrol_data, 0x05001828);
6448 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
6449 reg_val = R_REG(osh, &cc->pllcontrol_data);
6462 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6463 reg_val = R_REG(osh, &cc->pllcontrol_data);
6464 W_REG(osh, &cc->pllcontrol_data, ((reg_val & ~PMU1_PLL0_PC2_NDIV_INT_MASK)
6466 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6467 W_REG(osh, &cc->pllcontrol_data, ndiv_frac_int);
6480 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6481 W_REG(osh, &cc->pllcontrol_data, 0x01100014);
6482 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
6483 W_REG(osh, &cc->pllcontrol_data, 0x040C0C06);
6484 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6485 W_REG(osh, &cc->pllcontrol_data, 0x03140A08);
6486 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6487 W_REG(osh, &cc->pllcontrol_data, 0x00333333);
6488 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
6489 W_REG(osh, &cc->pllcontrol_data, 0x202C2820);
6490 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
6491 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
6493 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
6494 W_REG(osh, &cc->pllcontrol_data, 0x11100014);
6495 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
6496 W_REG(osh, &cc->pllcontrol_data, 0x040c0c06);
6497 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
6498 W_REG(osh, &cc->pllcontrol_data, 0x03000a08);
6499 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6500 W_REG(osh, &cc->pllcontrol_data, 0x00000000);
6501 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
6502 W_REG(osh, &cc->pllcontrol_data, 0x200005c0);
6503 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
6504 W_REG(osh, &cc->pllcontrol_data, 0x88888815);
6515 xtal_freq = si_pmu_alp_clock(sih, osh)/1000;
6520 W_REG(osh, &cc->pllcontrol_addr, PMU15_PLL_PLLCTL0);
6521 pll0 = R_REG(osh, &cc->pllcontrol_data);
6524 W_REG(osh, &cc->pllcontrol_data, pll0);
6546 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
6549 W_REG(osh, &cc->pllcontrol_data, 0x80BFA863);
6552 W_REG(osh, &cc->pllcontrol_data, 0x80AB1F7D);
6555 W_REG(osh, &cc->pllcontrol_data, 0x80b1f7c9);
6558 W_REG(osh, &cc->pllcontrol_data, 0x80c680af);
6561 W_REG(osh, &cc->pllcontrol_data, 0x80B8D016);
6564 W_REG(osh, &cc->pllcontrol_data, 0x80CD58FC);
6567 W_REG(osh, &cc->pllcontrol_data, 0x80D43149);
6570 W_REG(osh, &cc->pllcontrol_data, 0x80DB0995);
6573 W_REG(osh, &cc->pllcontrol_data, 0x80E1E1E2);
6576 W_REG(osh, &cc->pllcontrol_data, 0x80E8BA2F);
6591 tmp |= R_REG(osh, &cc->pmucontrol);
6592 W_REG(osh, &cc->pmucontrol, tmp);
6596 si_pmu_cal_fvco(si_t *sih, osl_t *osh)
6608 xf = si_pmu_alp_clock(sih, osh)/1000;
6655 si_pmu_gband_spurwar(si_t *sih, osl_t *osh)
6669 cc_clk_ctl_st = R_REG(osh, &cc->clk_ctl_st);
6670 AND_REG(osh, &cc->clk_ctl_st, ~(CCS_FORCEHT | CCS_HTAREQ));
6672 minmask = R_REG(osh, &cc->min_res_mask);
6673 maxmask = R_REG(osh, &cc->max_res_mask);
6677 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4322_HT_SI_AVAIL)));
6678 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4322_HT_SI_AVAIL)));
6679 SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL, PMU_MAX_TRANSITION_DLY);
6680 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4322_SI_PLL_ON)));
6681 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4322_SI_PLL_ON)));
6683 ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
6686 W_REG(osh, &cc->pllcontrol_addr, PMU2_PLL_PLLCTL2);
6687 W_REG(osh, &cc->pllcontrol_data, (R_REG(osh, &cc->pllcontrol_data) &
6694 W_REG(osh, &cc->pllcontrol_addr, PMU2_PLL_PLLCTL5);
6695 W_REG(osh, &cc->pllcontrol_data, (R_REG(osh, &cc->pllcontrol_data) &
6705 W_REG(osh, &cc->pmucontrol, R_REG(osh, &cc->pmucontrol) | PCTL_PLL_PLLCTL_UPD);
6709 W_REG(osh, &cc->max_res_mask, maxmask);
6711 W_REG(osh, &cc->min_res_mask, minmask);
6714 SPINWAIT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL), PMU_MAX_TRANSITION_DLY);
6715 ASSERT((R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
6718 W_REG(osh, &cc->clk_ctl_st, cc_clk_ctl_st);
6726 si_pmu_is_otp_powered(si_t *sih, osl_t *osh)
6742 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4322_OTP_PU)) != 0;
6745 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4325_OTP_PU)) != 0;
6748 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4329_OTP_PU)) != 0;
6751 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4315_OTP_PU)) != 0;
6754 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4319_OTP_PU)) != 0;
6758 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4336_OTP_PU)) != 0;
6761 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES43239_OTP_PU)) != 0;
6764 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4330_OTP_PU)) != 0;
6768 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4314_OTP_PU)) != 0;
6771 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES43143_OTP_PU)) != 0;
6774 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4334_OTP_PU)) != 0;
6779 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4324_OTP_PU)) != 0;
6783 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4335_OTP_PU)) != 0;
6786 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4350_OTP_PU)) != 0;
6792 st = (R_REG(osh, &cc->res_state) & PMURES_BIT(RES4360_OTP_PU)) != 0;
6819 si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable)
6821 BCMATTACHFN(si_pmu_sprom_enable)(si_t *sih, osl_t *osh, bool enable)
6838 W_REG(osh, &cc->chipcontrol_addr, 0);
6839 val = R_REG(osh, &cc->chipcontrol_data);
6844 W_REG(osh, &cc->chipcontrol_data, val);
6857 si_pmu_is_sprom_enabled(si_t *sih, osl_t *osh)
6859 BCMATTACHFN(si_pmu_is_sprom_enabled)(si_t *sih, osl_t *osh)
6877 W_REG(osh, &cc->chipcontrol_addr, 0);
6878 if (R_REG(osh, &cc->chipcontrol_data) & 0x80000000)
6891 BCMATTACHFN(si_pmu_set_lpoclk)(si_t *sih, osl_t *osh)
6914 ext_lpo_avail = R_REG(osh, &cc->pmustatus) & EXT_LPO_AVAIL;
6917 ext_lpo_avail = R_REG(osh, &cc->pmustatus) & EXT_LPO_AVAIL;
6932 lpo_sel = R_REG(osh, &cc->pmucontrol) & LPO_SEL;
6936 lpo_sel = R_REG(osh, &cc->pmucontrol) & LPO_SEL;
6963 lpo_sel = R_REG(osh, &cc->pmucontrol) & LPO_SEL;
6967 lpo_sel = R_REG(osh, &cc->pmucontrol) & LPO_SEL;
6987 BCMATTACHFN(si_pmu_chip_init)(si_t *sih, osl_t *osh)
6993 si_pmu_otp_chipcontrol(sih, osh);
7001 si_pmu_sprom_enable(sih, osh, FALSE);
7078 W_REG(osh, &cc->chipcontrol_addr, PMU_CHIPCTL3);
7079 tmp = R_REG(osh, &cc->chipcontrol_data);
7082 W_REG(osh, &cc->chipcontrol_data, tmp);
7115 si_pmu_set_lpoclk(sih, osh);
7128 BCMATTACHFN(si_pmu_swreg_init)(si_t *sih, osl_t *osh)
7141 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_PWM, 0xf);
7143 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_BURST, 0xf);
7146 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_PWM, 0xb);
7148 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_BURST, 0xb);
7150 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO1, 0x1);
7153 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO2_SEL, 0x1);
7168 W_REG(osh, &cc->regcontrol_addr, 4);
7169 val = R_REG(osh, &cc->regcontrol_data);
7171 W_REG(osh, &cc->regcontrol_data, val);
7180 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_PWM, 0xe);
7182 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_BURST, 0xe);
7184 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO1, 0xe);
7188 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_PWM, 0x16);
7190 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_BURST, 0x16);
7191 si_pmu_set_ldo_voltage(sih, osh, SET_LNLDO_PWERUP_LATCH_CTRL, 0x3);
7206 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_PWM, vreg_val);
7207 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_BURST, vreg_val);
7213 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LDO2, 0);
7225 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_PWM, 0x2);
7226 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_BURST, 0x2);
7228 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO1, 0x7);
7236 si_pmu_otp_regcontrol(sih, osh);
7283 si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, uint32 clk, uint32 delay_val)
7296 SPINWAIT(((R_REG(osh, &cc->pmustatus) & clk) != clk), delay_val);
7301 return (R_REG(osh, &cc->pmustatus) & clk);
7312 BCMATTACHFN(si_pmu_measure_alpclk)(si_t *sih, osl_t *osh)
7332 pmustat_lpo = !(R_REG(osh, &cc->pmucontrol) & PCTL_LPO_SEL);
7334 pmustat_lpo = R_REG(osh, &cc->pmustatus) & PST_EXTLPOAVAIL;
7340 W_REG(osh, &cc->pmu_xtalfreq, 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
7346 ilp_ctr = R_REG(osh, &cc->pmu_xtalfreq) & PMU_XTALFREQ_REG_ILPCTR_MASK;
7349 W_REG(osh, &cc->pmu_xtalfreq, 0);
7414 si_pmu_res_minmax_update(si_t *sih, osl_t *osh)
7439 W_REG(osh, &cc->min_res_mask, min_mask);
7442 W_REG(osh, &cc->max_res_mask, max_mask);