Lines Matching refs:AND_REG
2440 AND_REG(osh, &cc->res_dep_mask,
2675 AND_REG(osh, &cc->min_res_mask, ~PMURES_BIT(RES4328_BB_PLL_PU));
2676 AND_REG(osh, &cc->max_res_mask, ~PMURES_BIT(RES4328_BB_PLL_PU));
2679 AND_REG(osh, &cc->min_res_mask, ~PMURES_BIT(RES5354_BB_PLL_PU));
2680 AND_REG(osh, &cc->max_res_mask, ~PMURES_BIT(RES5354_BB_PLL_PU));
3424 AND_REG(osh, &cc->min_res_mask,
3451 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4313_HT_AVAIL_RSRC)));
3454 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4313_HT_AVAIL_RSRC)));
3929 AND_REG(osh, &cc->min_res_mask, ~ht_req);
3930 AND_REG(osh, &cc->max_res_mask, ~ht_req);
3977 AND_REG(osh, &cc->min_res_mask, ~ht_req);
3978 AND_REG(osh, &cc->max_res_mask, ~ht_req);
4186 AND_REG(osh, &cc->min_res_mask,
4188 AND_REG(osh, &cc->max_res_mask,
4195 AND_REG(osh, &cc->min_res_mask,
4197 AND_REG(osh, &cc->max_res_mask,
4203 AND_REG(osh, &cc->min_res_mask,
4205 AND_REG(osh, &cc->max_res_mask,
4425 AND_REG(osh, &cc->min_res_mask,
4427 AND_REG(osh, &cc->max_res_mask,
4435 AND_REG(osh, &cc->min_res_mask,
4437 AND_REG(osh, &cc->max_res_mask,
4463 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4315_HT_AVAIL)));
4464 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4315_HT_AVAIL)));
4467 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4315_BBPLL_PWRSW_PU)));
4468 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4315_BBPLL_PWRSW_PU)));
4484 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4319_HT_AVAIL)));
4485 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4319_HT_AVAIL)));
4488 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
4489 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
4501 AND_REG(osh, &cc->min_res_mask,
4503 AND_REG(osh, &cc->max_res_mask,
4511 AND_REG(osh, &cc->min_res_mask,
4513 AND_REG(osh, &cc->max_res_mask,
4614 AND_REG(osh, &cc->clkstretch, ~CSTRETCH_HT);
4917 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4322_HT_SI_AVAIL)));
4918 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4322_HT_SI_AVAIL)));
4920 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4322_SI_PLL_ON)));
4921 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4322_SI_PLL_ON)));
5663 AND_REG(osh, &cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
5854 AND_REG(osh, &cc->min_res_mask, ~(rsrcs | deps));
5892 AND_REG(osh, &cc->chipcontrol_data, ~0x04);
5947 AND_REG(osh, &cc->chipcontrol_data, ~0x04);
5959 AND_REG(osh, &cc->chipcontrol_data, ~0x04);
6000 AND_REG(osh, &cc->chipcontrol_data, ~0x04);
6670 AND_REG(osh, &cc->clk_ctl_st, ~(CCS_FORCEHT | CCS_HTAREQ));
6677 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4322_HT_SI_AVAIL)));
6678 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4322_HT_SI_AVAIL)));
6680 AND_REG(osh, &cc->min_res_mask, ~(PMURES_BIT(RES4322_SI_PLL_ON)));
6681 AND_REG(osh, &cc->max_res_mask, ~(PMURES_BIT(RES4322_SI_PLL_ON)));