Lines Matching defs:freq_tgt
3161 uint32 freq_tgt; /* freq_target: N_divide_ratio bitfield in DFLL */
3165 * If a DFLL clock of 480Mhz is desired, use this table to determine xf and freq_tgt for
4152 uint32 freq_tgt, pll0;
4173 freq_tgt = (pll0 & PMU15_PLL_PC0_FREQTGT_MASK) >> PMU15_PLL_PC0_FREQTGT_SHIFT;
4174 if (freq_tgt == xt->freq_tgt) {
4215 pll0 = (pll0 & ~PMU15_PLL_PC0_FREQTGT_MASK) | (xt->freq_tgt << PMU15_PLL_PC0_FREQTGT_SHIFT);
4223 hsic_freq = pmu2_xtaltab0_adfll_480[xt_idx].freq_tgt;
4246 uint32 freq_tgt = 0, pll0 = 0;
4255 freq_tgt = (pll0 & PMU15_PLL_PC0_FREQTGT_MASK) >> PMU15_PLL_PC0_FREQTGT_SHIFT;
4263 if (xt->freq_tgt == freq_tgt)
4269 if (xt->freq_tgt == freq_tgt)
4283 uint32 freq_tgt, pll0;
4288 freq_tgt = (pll0 & PMU15_PLL_PC0_FREQTGT_MASK) >> PMU15_PLL_PC0_FREQTGT_SHIFT;
4292 if (xt->freq_tgt == freq_tgt)
4299 if (xt->freq_tgt == freq_tgt)
6523 pll0 |= (xt->freq_tgt << PMU15_PLL_PC0_FREQTGT_SHIFT);