Lines Matching refs:osh
79 osl_t *osh;
86 osh = si_osh(sih);
96 if (R_REG(osh, &((mips74kregs_t *)regs)->intmask[irq]) &
104 sbipsflag = R_REG(osh, &sb->sbipsflag);
141 osl_t *osh;
145 osh = si_osh(sih);
148 W_REG(osh, &((mips74kregs_t *)regs)->intmask[irq], 0);
152 W_REG(osh, &sb->sbintvec, 0);
154 OR_REG(osh, &sb->sbipsflag, sbips_int_mask[irq]);
168 osl_t *osh;
174 osh = si_osh(sih);
185 AND_REG(osh, &((mips74kregs_t *)regs)->intmask[0], ~(1 << flag));
188 OR_REG(osh, &((mips74kregs_t *)regs)->intmask[0], 1 << flag);
190 W_REG(osh, &((mips74kregs_t *)regs)->intmask[irq], 1 << flag);
196 AND_REG(osh, &sb->sbintvec, ~(1 << flag));
199 OR_REG(osh, &sb->sbintvec, 1 << flag);
203 flag |= R_REG(osh, &sb->sbipsflag) & ~sbips_int_mask[irq];
204 W_REG(osh, &sb->sbipsflag, flag);
219 osl_t *osh;
225 osh = si_osh(sih);
246 W_REG(osh, &cc->flash_waitcount, tmp);
250 W_REG(osh, &cc->pcmcia_memwait, tmp);
332 osl_t *osh;
339 osh = si_osh(sih);
342 return si_pmu_cpu_clock(sih, osh);
352 n = R_REG(osh, &cc->clockcontrol_n);
357 m = R_REG(osh, &cc->clockcontrol_m3);
368 m = R_REG(osh, &cc->clockcontrol_m2);
370 m = R_REG(osh, &cc->clockcontrol_sb);
388 osl_t *osh;
390 osh = si_osh(sih);
393 return si_pmu_mem_clock(sih, osh);
762 osl_t *osh;
765 osh = si_osh(sih);
784 W_REG(osh, &cc->jtagctrl, 0x01);
785 W_REG(osh, &cc->jtagcmd, 0x80030000);
786 W_REG(osh, &cc->gpioouten, 0x0);
789 W_REG(osh, &cc->gpioouten, 0x0);
790 W_REG(osh, &cc->chipcontrol_addr, 0x2);
791 W_REG(osh, &cc->chipcontrol_data, 0x04000600);
795 W_REG(osh, &cc->watchdog, reset*ILP_CLOCK);
814 osl_t *osh;
848 osh = si_osh(sih);
874 W_REG(osh, &cc->pllcontrol_addr, PMU6_4706_PROCPLL_OFF + i);
875 (void)R_REG(osh, &cc->pllcontrol_addr);
876 if (R_REG(osh, &cc->pllcontrol_data) != pll_table[idx][i + 3]) {
877 W_REG(osh, &cc->pllcontrol_data, pll_table[idx][i + 3]);
886 (void)R_REG(osh, &cc->pllcontrol_data);
889 W_REG(osh, &cc->pmucontrol,
890 R_REG(osh, &cc->pmucontrol) | PCTL_PLL_PLLCTL_UPD);
911 osl_t *osh;
1048 osh = si_osh(sih);
1082 (((chippkg = R_REG(osh, &cc->sromotp[23])) & 0x80) == 0x80)) {
1102 W_REG(osh, &cc->pllcontrol_addr, mainpll_pll0 + i);
1103 (void)R_REG(osh, &cc->pllcontrol_addr);
1104 if (R_REG(osh, &cc->pllcontrol_data) != pll_table[idx][i + 3])
1116 W_REG(osh, &cc->pllcontrol_addr, mainpll_pll0 + i);
1117 (void)R_REG(osh, &cc->pllcontrol_addr);
1119 W_REG(osh, &cc->pllcontrol_data, tmp);
1122 (void)R_REG(osh, &cc->pllcontrol_data);
1126 W_REG(osh, &cc->min_res_mask,
1127 R_REG(osh, &cc->min_res_mask) & ~RES4716_PROC_HT_AVAIL);
1130 W_REG(osh, &cc->watchdog, 1000);
1133 W_REG(osh, &cc->pmucontrol,
1134 R_REG(osh, &cc->pmucontrol) | PCTL_PLL_PLLCTL_UPD);
1188 osl_t *osh;
1404 osh = si_osh(sih);
1431 orig_n = R_REG(osh, clockcontrol_n);
1432 orig_sb = R_REG(osh, clockcontrol_sb);
1433 orig_pci = R_REG(osh, clockcontrol_pci);
1457 orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
1464 W_REG(osh, clockcontrol_n, type3_table[i].n);
1465 W_REG(osh, clockcontrol_m2, type3_table[i].m2);
1480 orig_mips = R_REG(osh, &cc->clockcontrol_m3);
1493 W_REG(osh, &cc->clockcontrol_m3, new_mips);
1514 orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
1557 W_REG(osh, clockcontrol_n, te->n);
1558 W_REG(osh, clockcontrol_sb, te->sb);
1559 W_REG(osh, clockcontrol_pci, te->pci33);
1560 W_REG(osh, &cc->clockcontrol_m2, te->m2);
1561 W_REG(osh, &cc->clockcontrol_m3, te->m3);
1566 W_REG(osh, &cc->chipcontrol,
1567 R_REG(osh, &cc->chipcontrol) | 0x100);
1613 W_REG(osh, &cc->watchdog, 20);
1614 (void) R_REG(osh, &cc->chipid);
1647 W_REG(osh, &mipsr->intmask, 1);
1655 W_REG(osh, &mipsr->timer, 100);
1656 (void) R_REG(osh, &mipsr->timer);
1682 W_REG(osh, &cc->watchdog, 20);
1683 (void) R_REG(osh, &cc->chipid);
1774 osl_t *osh;
1780 osh = si_osh(sih);
1790 config = R_REG(osh, &memc->config);
1791 wr = R_REG(osh, &memc->wrncdlcor);
1792 rd = R_REG(osh, &memc->rdncdlcor);
1793 misc = R_REG(osh, &memc->miscdlyctl);
1794 dqsg = R_REG(osh, &memc->dqsgatencdl);