• Home
  • History
  • Annotate
  • Raw
  • Download
  • only in /netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/shared/

Lines Matching refs:d64rxregs

48 #define d64rxregs	dregs.d64_u.rxregs_64
481 di->d64rxregs = (dma64regs_t *)dmaregsrx;
538 W_REG(di->osh, &di->d64rxregs->addrlow, 0xffffffff);
539 mask = R_REG(di->osh, &di->d64rxregs->addrlow);
542 mask = R_REG(di->osh, &di->d64rxregs->ptr) | 0xf;
555 &di->d64rxregs->control) & D64_RC_BL_MASK) >> D64_RC_BL_SHIFT;
557 &di->d64rxregs->control) & D64_RC_PC_MASK) >>
560 &di->d64rxregs->control) & D64_RC_PT_MASK) >>
927 } else if (di->d64rxregs != NULL) {
928 W_REG(di->osh, &di->d64rxregs->addrlow, 0xff0);
929 addrl = R_REG(di->osh, &di->d64rxregs->addrlow);
952 } else if (di->d64rxregs != NULL) {
953 if (!_dma64_addrext(di->osh, di->d64rxregs)) {
991 W_REG(di->osh, &di->d64rxregs->addrlow, (PHYSADDRLO(pa) +
993 W_REG(di->osh, &di->d64rxregs->addrhigh, (PHYSADDRHI(pa) +
1013 W_REG(di->osh, &di->d64rxregs->addrlow, (PHYSADDRLO(pa) +
1015 W_REG(di->osh, &di->d64rxregs->addrhigh, di->ddoffsethigh);
1016 SET_REG(di->osh, &di->d64rxregs->control, D64_RC_AE,
1114 uint32 control = (R_REG(di->osh, &di->d64rxregs->control) & D64_RC_AE) | D64_RC_RE;
1135 W_REG(di->osh, &di->d64rxregs->control,
1191 dma64regs_t *dregs = di->d64rxregs;
1415 W_REG(di->osh, &di->d64rxregs->ptr, di->rcvptrbase + I2B(rxout, dma64dd_t));
1524 end = (uint16)B2I(((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_CD_MASK) -
1645 curr = B2I(((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_CD_MASK) -
1647 ptr = B2I(((R_REG(di->osh, &di->d64rxregs->ptr) & D64_RS0_CD_MASK) -
1889 R_REG(di->osh, &di->d64rxregs->control),
1890 R_REG(di->osh, &di->d64rxregs->addrlow),
1891 R_REG(di->osh, &di->d64rxregs->addrhigh),
1892 R_REG(di->osh, &di->d64rxregs->ptr),
1893 R_REG(di->osh, &di->d64rxregs->status0),
1894 R_REG(di->osh, &di->d64rxregs->status1));
2653 return ((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_RS_MASK) == D64_RS0_RS_STOPPED);
2768 return ((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_CD_MASK) ==
2769 (R_REG(di->osh, &di->d64rxregs->ptr) & D64_RS0_CD_MASK));
2780 W_REG(di->osh, &di->d64rxregs->control, 0);
2781 SPINWAIT(((status = (R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_RS_MASK)) !=
2792 rc = R_REG(di->osh, &di->d64rxregs->control);
2830 cur_idx = B2I(((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_CD_MASK) -
3197 curr = (uint16)B2I(((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_CD_MASK) -
3383 status1 = R_REG(di->osh, &di->d64rxregs->status1);
3448 dma64regs_t *dregs = di->d64rxregs;