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  • only in /netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/shared/

Lines Matching defs:val16

398 		uint16 val16;
427 bytes.val16 = htol16(*(uint16 *)val);
450 uint16 val16;
479 *(uint16 *)val = ltoh16(bytes.val16);
513 uint16 cmd16, val16;
535 val16 = ptr[7];
536 val16 = ((val16 << 8) | ptr[6]);
537 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA3, val16);
541 val16 = ptr[5];
542 val16 = ((val16 << 8) | ptr[4]);
543 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA2, val16);
544 val16 = ptr[3];
545 val16 = ((val16 << 8) | ptr[2]);
546 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA1, val16);
547 val16 = ptr[1];
548 val16 = ((val16 << 8) | ptr[0]);
549 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA0, val16);
553 val16 = (uint16)((*(uint32 *)val) >> 16);
554 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA1, val16);
555 val16 = (uint16)(*(uint32 *)val);
556 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA0, val16);
560 val16 = *(uint16 *)val;
561 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA0, val16);
565 val16 = *(uint8 *)val;
566 robo->miiwr(h, PSEUDO_PHYAD, REG_MII_DATA0, val16);
577 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_ADDR);
578 if ((val16 & 3) == 0)
594 uint16 cmd16, val16;
618 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_ADDR);
619 if ((val16 & 3) == 0)
630 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA3);
631 ptr[7] = (val16 >> 8);
632 ptr[6] = (val16 & 0xff);
636 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA2);
637 ptr[5] = (val16 >> 8);
638 ptr[4] = (val16 & 0xff);
639 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA1);
640 ptr[3] = (val16 >> 8);
641 ptr[2] = (val16 & 0xff);
642 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA0);
643 ptr[1] = (val16 >> 8);
644 ptr[0] = (val16 & 0xff);
648 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA1);
649 *(uint32 *)val = (((uint32)val16) << 16);
650 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA0);
651 *(uint32 *)val |= val16;
655 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA0);
656 *(uint16 *)val = val16;
660 val16 = robo->miird(h, PSEUDO_PHYAD, REG_MII_DATA0);
661 *(uint8 *)val = (uint8)(val16 & 0xff);
777 uint16 val16;
795 val16 = ptr[7];
796 val16 = ((val16 << 8) | ptr[6]);
797 val_h = val16 << 16;
801 val16 = ptr[5];
802 val16 = ((val16 << 8) | ptr[4]);
803 val_h |= val16;
805 val16 = ptr[3];
806 val16 = ((val16 << 8) | ptr[2]);
807 val_l = val16 << 16;
808 val16 = ptr[1];
809 val16 = ((val16 << 8) | ptr[0]);
810 val_l |= val16;
1402 uint16 val16;
1545 val16 = ((0 << 13) | /* priority - always 0 */
1548 &val16, sizeof(val16));
1585 val16 = 0xc008;
1587 &val16, sizeof(val16));
1620 val16 = ((1 << 13) | /* start command */
1623 robo->ops->write_reg(robo, PAGE_VLAN, REG_VLAN_ACCESS, &val16,
1624 sizeof(val16));
1645 val16 = vid; /* vlan id */
1646 robo->ops->write_reg(robo, PAGE_VTBL, vtbli, &val16,
1647 sizeof(val16));
1685 val16 = 0x11f;
1686 robo->ops->write_reg(robo, 0x30, 0x4, &val16, sizeof(val16));
1691 val16 = ((1 << 0) | /* Pri 0 mapped to TXQ 1 */
1699 robo->ops->write_reg(robo, 0x30, 0x62, &val16, sizeof(val16));
1762 uint16 val16;
1767 robo->ops->read_reg(robo, 0x34, 0x20, &val16, sizeof(val16));
1768 val16 = (val16 & 0xF000) | WAN_VLAN_ENTRY_IDX;
1769 robo->ops->write_reg(robo, 0x34, 0x20, &val16, sizeof(val16));
1770 ET_ERROR(("Alex:P:0x34 A:0x20 val16=%x\n",val16));
1790 robo->ops->read_reg(robo, 0x4, 0xE, &val16, sizeof(val16));
1791 val16 |= 0x0AAA;
1792 robo->ops->write_reg(robo, 0x4, 0xE, &val16, sizeof(val16));
1794 ET_ERROR(("Alex:P:0x4 A:0xE val16=%x\n",val16));
2257 uint16 val16;
2268 val16 = 0xa800;
2269 robo->miiwr(robo->h, phy, REG_MII_AUTO_PWRDOWN, val16);
2277 val16 = robo->miird(robo->h, phy, REG_MII_BRCM_TEST);
2279 (val16 | (1 << 7)));
2284 val16 = robo->miird(robo->h, phy, REG_MII_AUX_STATUS2);
2286 (val16 & ~(1 << 5)));
2289 val16 = robo->miird(robo->h, phy, REG_MII_BRCM_TEST);
2291 (val16 & ~(1 << 7)));
2304 uint16 val16;
2311 val16 = robo->miird(robo->h, phy, REG_MII_CTRL);
2312 val16 &= 0xf7ff;
2313 robo->miiwr(robo->h, phy, REG_MII_CTRL, val16);
2315 robo->ops->read_reg(robo, 0x10+phy, 0x00, &val16, sizeof(val16));
2316 val16 &= 0xf7ff;
2317 robo->ops->write_reg(robo, 0x10+phy, 0x00, &val16, sizeof(val16));
2430 uint16 val16;
2449 val16 = robo->miird(robo->h, phy, REG_MII_BRCM_TEST);
2451 (val16 | (1 << 7)));
2456 val16 = robo->miird(robo->h, phy, REG_MII_AUX_STATUS2);
2458 (val16 | (1 << 5)));
2461 val16 = robo->miird(robo->h, phy, REG_MII_BRCM_TEST);
2463 (val16 & ~(1 << 7)));
2479 uint16 val16;
2483 &val16, sizeof(val16));
2484 if (val16 & (0x1 << phy))
2493 val16 = robo->miird(robo->h, phy, REG_MII_CTRL);
2494 robo->miiwr(robo->h, phy, REG_MII_CTRL, val16 | 0x800);
2496 robo->ops->read_reg(robo, 0x10+phy, 0x00, &val16, sizeof(val16));
2497 val16 |= 0x800;
2498 robo->ops->write_reg(robo, 0x10+phy, 0x00, &val16, sizeof(val16));
2729 uint16 val16;
2734 val16 = 0;
2735 robo->ops->read_reg(robo, 0x92, 0x00, &val16, sizeof(val16));
2736 if (val16 == 0x1f) {
2748 val16 = robo->miird(robo->h, phy, REG_MII_CLAUSE_45_CTL2);
2749 val16 &= ~0x6;
2757 robo->miiwr(robo->h, phy, REG_MII_CLAUSE_45_CTL2, val16);