Lines Matching refs:sii
37 (sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
42 (sii->coreid[sii->curidx] == USB20H_CORE_ID))
44 (sii->coreid[sii->curidx] == NS_CCB_CORE_ID))
118 ai_hwfixup(si_info_t *sii)
128 if (BUSTYPE(sii->pub.bustype) == SI_BUS &&
129 ((CHIPID(sii->pub.chip) == BCM4716_CHIP_ID) ||
130 (CHIPID(sii->pub.chip) == BCM4748_CHIP_ID))) {
133 ASSERT(sii->coreid[3] == MIPS74K_CORE_ID);
134 cpu = REG_MAP(sii->wrapba[3], SI_CORE_SIZE);
135 ASSERT(sii->coreid[5] == PCIE_CORE_ID);
136 pcie = REG_MAP(sii->wrapba[5], SI_CORE_SIZE);
137 ASSERT(sii->coreid[8] == I2S_CORE_ID);
138 i2s = REG_MAP(sii->wrapba[8], SI_CORE_SIZE);
139 if ((R_REG(sii->osh, &cpu->oobselina74) != 0x08060504) ||
140 (R_REG(sii->osh, &pcie->oobselina74) != 0x08060504) ||
141 (R_REG(sii->osh, &i2s->oobselouta30) != 0x88)) {
145 W_REG(sii->osh, &cpu->oobselina74, 0x07060504);
146 W_REG(sii->osh, &pcie->oobselina74, 0x07060504);
147 W_REG(sii->osh, &i2s->oobselouta30, 0x87);
205 si_info_t *sii = SI_INFO(sih);
206 uint i, coreid = sii->coreid[sii->curidx];
229 si_info_t *sii = SI_INFO(sih);
233 erombase = R_REG(sii->osh, &cc->eromptr);
242 sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
245 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
276 SI_VMSG(("Found END of erom after %d cores\n", sii->numcores));
277 ai_hwfixup(sii);
312 sii->oob_router = addrl;
319 idx = sii->numcores;
321 sii->cia[idx] = cia;
322 sii->cib[idx] = cib;
323 sii->coreid[idx] = remap_coreid(sih, cid);
363 sii->coresba[idx] = addrl;
364 sii->coresba_size[idx] = sizel;
371 sii->coresba2[idx] = addrl;
372 sii->coresba2_size[idx] = sizel;
407 sii->wrapba[idx] = addrl;
424 sii->wrapba[idx] = addrl;
429 i = (R_REG(sii->osh, &cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
433 for (j = 0; j < sii->numcores; j++) {
434 if (sii->coreid[j] == GMAC_CORE_ID)
437 if (j != sii->numcores) {
450 sii->numcores++;
456 sii->numcores = 0;
466 si_info_t *sii = SI_INFO(sih);
470 if (coreidx >= MIN(sii->numcores, SI_MAXCORES))
473 addr = sii->coresba[coreidx];
474 wrap = sii->wrapba[coreidx];
480 ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
485 if (!sii->regs[coreidx]) {
486 sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
487 ASSERT(GOODREGS(sii->regs[coreidx]));
489 sii->curmap = regs = sii->regs[coreidx];
490 if (!sii->wrappers[coreidx] && (wrap != 0)) {
491 sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
492 ASSERT(GOODREGS(sii->wrappers[coreidx]));
494 sii->curwrap = sii->wrappers[coreidx];
499 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, addr);
500 regs = sii->curmap;
502 if (PCIE_GEN2(sii))
503 OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_WIN2, 4, wrap);
505 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, wrap);
510 sii->curmap = regs = (void *)((uintptr)addr);
511 sii->curwrap = (void *)((uintptr)wrap);
522 sii->curmap = regs;
523 sii->curidx = coreidx;
531 si_info_t *sii = SI_INFO(sih);
538 for (i = 0; i < sii->numcores; i++) {
539 if (sii->coreid[i] == CC_CORE_ID) {
540 cc = (chipcregs_t *)sii->regs[i];
547 erombase = R_REG(sii->osh, &cc->eromptr);
551 cidx = sii->curidx;
552 cia = sii->cia[cidx];
553 cib = sii->cib[cidx];
624 si_info_t *sii;
627 sii = SI_INFO(sih);
628 cidx = sii->curidx;
631 return sii->coresba[cidx];
633 return sii->coresba2[cidx];
645 si_info_t *sii;
648 sii = SI_INFO(sih);
649 cidx = sii->curidx;
652 return sii->coresba_size[cidx];
654 return sii->coresba2_size[cidx];
665 si_info_t *sii;
668 sii = SI_INFO(sih);
671 return sii->curidx;
675 return sii->curidx;
680 return sii->curidx;
682 ai = sii->curwrap;
684 return (R_REG(sii->osh, &ai->oobselouta30) & 0x1f);
690 si_info_t *sii;
693 sii = SI_INFO(sih);
696 return sii->curidx;
700 return sii->curidx;
705 return sii->curidx;
707 ai = sii->curwrap;
709 return ((R_REG(sii->osh, &ai->oobselouta30) >> AI_OOBSEL_1_SHIFT) & AI_OOBSEL_MASK);
720 si_info_t *sii = SI_INFO(sih);
721 uint32 *map = (uint32 *) sii->curwrap;
724 uint32 w = R_REG(sii->osh, map+(offset/4));
727 W_REG(sii->osh, map+(offset/4), w);
730 return (R_REG(sii->osh, map+(offset/4)));
736 si_info_t *sii;
739 sii = SI_INFO(sih);
740 cia = sii->cia[sii->curidx];
747 si_info_t *sii;
750 sii = SI_INFO(sih);
751 cib = sii->cib[sii->curidx];
758 si_info_t *sii;
761 sii = SI_INFO(sih);
762 ai = sii->curwrap;
764 return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) == SICF_CLOCK_EN) &&
765 ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
785 si_info_t *sii;
787 sii = SI_INFO(sih);
800 if (!sii->regs[coreidx]) {
801 sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
803 ASSERT(GOODREGS(sii->regs[coreidx]));
805 r = (uint32 *)((uchar *)sii->regs[coreidx] + regoff);
809 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
813 r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
814 } else if (sii->pub.buscoreidx == coreidx) {
819 if (SI_FAST(sii))
820 r = (uint32 *)((char *)sii->curmap +
823 r = (uint32 *)((char *)sii->curmap +
831 INTR_OFF(sii, intr_val);
834 origidx = si_coreidx(&sii->pub);
837 r = (uint32*) ((uchar*) ai_setcoreidx(&sii->pub, coreidx) + regoff);
843 w = (R_REG(sii->osh, r) & ~mask) | val;
844 W_REG(sii->osh, r, w);
848 w = R_REG(sii->osh, r);
853 ai_setcoreidx(&sii->pub, origidx);
855 INTR_RESTORE(sii, intr_val);
864 si_info_t *sii;
869 sii = SI_INFO(sih);
871 ASSERT(GOODREGS(sii->curwrap));
872 ai = sii->curwrap;
875 if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
879 SPINWAIT(((status = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
885 SPINWAIT(((status = R_REG(sii->osh, &ai->resetstatus)) != 0), 10000);
890 W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
891 dummy = R_REG(sii->osh, &ai->resetctrl);
895 W_REG(sii->osh, &ai->ioctrl, bits);
896 dummy = R_REG(sii->osh, &ai->ioctrl);
909 si_info_t *sii;
914 sii = SI_INFO(sih);
915 ASSERT(GOODREGS(sii->curwrap));
916 ai = sii->curwrap;
919 SPINWAIT(((dummy = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
922 W_REG(sii->osh, &ai->ioctrl, (bits | resetbits | SICF_FGC | SICF_CLOCK_EN));
923 dummy = R_REG(sii->osh, &ai->ioctrl);
927 SPINWAIT(((dummy = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
931 W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
934 while (R_REG(sii->osh, &ai->resetctrl) != 0 && --loop_counter != 0) {
936 SPINWAIT(((dummy = R_REG(sii->osh, &ai->resetstatus)) != 0), 300);
940 W_REG(sii->osh, &ai->resetctrl, 0);
943 SPINWAIT((R_REG(sii->osh, &ai->resetstatus) != 0), 300);
947 W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
948 dummy = R_REG(sii->osh, &ai->ioctrl);
956 si_info_t *sii;
960 sii = SI_INFO(sih);
978 ASSERT(GOODREGS(sii->curwrap));
979 ai = sii->curwrap;
984 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
985 W_REG(sii->osh, &ai->ioctrl, w);
992 si_info_t *sii;
996 sii = SI_INFO(sih);
1013 ASSERT(GOODREGS(sii->curwrap));
1014 ai = sii->curwrap;
1019 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
1020 W_REG(sii->osh, &ai->ioctrl, w);
1023 return R_REG(sii->osh, &ai->ioctrl);
1029 si_info_t *sii;
1033 sii = SI_INFO(sih);
1050 ASSERT(GOODREGS(sii->curwrap));
1051 ai = sii->curwrap;
1057 w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
1058 W_REG(sii->osh, &ai->iostatus, w);
1061 return R_REG(sii->osh, &ai->iostatus);
1069 si_info_t *sii;
1074 sii = SI_INFO(sih);
1075 osh = sii->osh;
1077 for (i = 0; i < sii->numcores; i++) {
1078 si_setcoreidx(&sii->pub, i);
1079 ai = sii->curwrap;
1081 bcm_bprintf(b, "core 0x%x: \n", sii->coreid[i]);
1123 if ((sih->chip == BCM4331_CHIP_ID) && (sii->coreid[i] == PCIE_CORE_ID)) {
1125 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, 0x18103000);