Lines Matching refs:control_register
426 u32 control_register; /* cached value */
721 1 << ((hdspm_decode_latency(hdspm->control_register) + 8));
750 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
751 hdspm_write(s, HDSPM_controlRegister, s->control_register);
756 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
757 hdspm_write(s, HDSPM_controlRegister, s->control_register);
788 s->control_register &= ~HDSPM_LatencyMask;
789 s->control_register |= hdspm_encode_latency(n);
791 hdspm_write(s, HDSPM_controlRegister, s->control_register);
835 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
942 hdspm->control_register &= ~HDSPM_FrequencyMask;
943 hdspm->control_register |= rate_bits;
944 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1086 hmidi->hdspm->control_register |= HDSPM_Midi1InterruptEnable;
1088 hmidi->hdspm->control_register |= HDSPM_Midi0InterruptEnable;
1090 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, hmidi->hdspm->control_register);
1107 if (!(hdspm->control_register & ie)) {
1109 hdspm->control_register |= ie;
1112 hdspm->control_register &= ~ie;
1115 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1394 if (hdspm->control_register & HDSPM_ClockModeMaster)
1436 if (hdspm->control_register & HDSPM_ClockModeMaster) {
1471 hdspm->control_register &= ~HDSPM_ClockModeMaster;
1473 hdspm->control_register);
1508 hdspm->control_register |= HDSPM_ClockModeMaster;
1509 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1587 switch (hdspm->control_register & HDSPM_SyncRefMask) {
1601 switch (hdspm->control_register & HDSPM_SyncRefMask) {
1614 hdspm->control_register &= ~HDSPM_SyncRefMask;
1619 hdspm->control_register |= 0;
1622 hdspm->control_register |= HDSPM_SyncRef0;
1625 hdspm->control_register |= HDSPM_SyncRef1;
1628 hdspm->control_register |= HDSPM_SyncRef1+HDSPM_SyncRef0;
1631 hdspm->control_register |= HDSPM_SyncRef2;
1634 hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef0;
1637 hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef1;
1640 hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
1643 hdspm->control_register |= HDSPM_SyncRef3;
1651 hdspm->control_register |= HDSPM_SyncRef_MADI;
1654 hdspm->control_register |= HDSPM_SyncRef_Word;
1660 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1822 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
1829 hdspm->control_register |= HDSPM_LineOut;
1831 hdspm->control_register &= ~HDSPM_LineOut;
1832 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1886 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
1892 hdspm->control_register |= HDSPM_TX_64ch;
1894 hdspm->control_register &= ~HDSPM_TX_64ch;
1895 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1949 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
1955 hdspm->control_register |= HDSPM_clr_tms;
1957 hdspm->control_register &= ~HDSPM_clr_tms;
1958 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2012 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
2018 hdspm->control_register |= HDSPM_AutoInp;
2020 hdspm->control_register &= ~HDSPM_AutoInp;
2021 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2075 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
2081 hdspm->control_register |= HDSPM_Emphasis;
2083 hdspm->control_register &= ~HDSPM_Emphasis;
2084 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2138 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
2144 hdspm->control_register |= HDSPM_Dolby;
2146 hdspm->control_register &= ~HDSPM_Dolby;
2147 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2201 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
2207 hdspm->control_register |= HDSPM_Professional;
2209 hdspm->control_register &= ~HDSPM_Professional;
2210 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2264 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
2270 hdspm->control_register |= HDSPM_InputSelect0;
2272 hdspm->control_register &= ~HDSPM_InputSelect0;
2273 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2335 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
2341 hdspm->control_register |= HDSPM_DS_DoubleWire;
2343 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
2344 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2406 if (hdspm->control_register & HDSPM_QS_DoubleWire)
2408 if (hdspm->control_register & HDSPM_QS_QuadWire)
2415 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
2420 hdspm->control_register |= HDSPM_QS_DoubleWire;
2423 hdspm->control_register |= HDSPM_QS_QuadWire;
2426 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2999 hdspm->control_register, hdspm->control2_register,
3006 control_register &
3015 control_register & HDSPM_LineOut) ? "on " : "off",
3018 switch (hdspm->control_register & HDSPM_InputMask) {
3029 switch (hdspm->control_register & HDSPM_SyncRefMask) {
3045 control_register & HDSPM_clr_tms) ? "on" : "off",
3047 control_register & HDSPM_TX_64ch) ? "64" : "56",
3049 control_register & HDSPM_AutoInp) ? "on" : "off");
3077 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
3192 hdspm->control_register,
3199 control_register &
3208 control_register & HDSPM_LineOut) ? "on " : "off",
3214 control_register & HDSPM_clr_tms) ? "on" : "off",
3216 control_register & HDSPM_Emphasis) ? "on" : "off",
3218 control_register & HDSPM_Dolby) ? "on" : "off");
3255 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
3272 hdspm->control_register & HDSPM_DS_DoubleWire?
3275 hdspm->control_register & HDSPM_QS_DoubleWire?
3277 hdspm->control_register & HDSPM_QS_QuadWire?
3364 hdspm->control_register = HDSPM_ClockModeMaster | /* Master Cloack Mode on */
3370 hdspm->control_register = HDSPM_ClockModeMaster | /* Master Cloack Mode on */
3382 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3465 hdspm->control_register &= ~HDSPM_Midi0InterruptEnable;
3467 hdspm->control_register);
3473 hdspm->control_register &= ~HDSPM_Midi1InterruptEnable;
3475 hdspm->control_register);
4368 hdspm->control_register = 0;
4464 hdspm->control_register &=
4469 hdspm->control_register);