Lines Matching refs:rmh
53 struct pcxhr_rmh rmh;
55 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
57 rmh.cmd[0] |= IO_NUM_REG_IN_ANA_LEVEL;
58 rmh.cmd[2] = chip->analog_capture_volume[channel];
60 rmh.cmd[0] |= IO_NUM_REG_OUT_ANA_LEVEL;
65 rmh.cmd[2] = PCXHR_ANALOG_PLAYBACK_LEVEL_MAX - vol; /* playback analog levels are inversed */
67 rmh.cmd[1] = 1 << ((2 * chip->chip_idx) + channel); /* audio mask */
68 rmh.cmd_len = 3;
69 err = pcxhr_send_msg(chip->mgr, &rmh);
209 struct pcxhr_rmh rmh;
222 pcxhr_init_rmh(&rmh, CMD_STREAM_OUT_LEVEL_ADJUST);
224 pcxhr_set_pipe_cmd_params(&rmh, 0, pipe->first_audio, 0, 1<<idx);
226 rmh.cmd[0] |= MORE_THAN_ONE_STREAM_LEVEL;
227 rmh.cmd[2] = VALID_STREAM_PAN_LEVEL_MASK | VALID_STREAM_LEVEL_1_MASK;
228 rmh.cmd[2] |= (left << 10);
229 rmh.cmd[3] = VALID_STREAM_PAN_LEVEL_MASK | VALID_STREAM_LEVEL_2_MASK;
230 rmh.cmd[3] |= right;
231 rmh.cmd_len = 4;
233 err = pcxhr_send_msg(chip->mgr, &rmh);
252 struct pcxhr_rmh rmh;
260 pcxhr_init_rmh(&rmh, CMD_AUDIO_LEVEL_ADJUST);
262 pcxhr_set_pipe_cmd_params(&rmh, capture, 0, 0, 1 << (channel + pipe->first_audio));
267 rmh.cmd[0] |= VALID_AUDIO_IO_DIGITAL_LEVEL;
269 rmh.cmd[2] = chip->digital_capture_volume[channel];
271 rmh.cmd[0] |= VALID_AUDIO_IO_MONITOR_LEVEL | VALID_AUDIO_IO_MUTE_MONITOR_1;
275 rmh.cmd[2] = chip->monitoring_volume[channel] << 10;
277 rmh.cmd[2] |= AUDIO_IO_HAS_MUTE_MONITOR_1;
279 rmh.cmd_len = 3;
281 err = pcxhr_send_msg(chip->mgr, &rmh);
517 struct pcxhr_rmh rmh;
541 pcxhr_init_rmh(&rmh, CMD_RESYNC_AUDIO_INPUTS);
542 rmh.cmd[0] |= (1 << chip->chip_idx);
543 err = pcxhr_send_msg(chip->mgr, &rmh);
547 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set codec SRC on off */
548 rmh.cmd_len = 3;
549 rmh.cmd[0] |= IO_NUM_UER_CHIP_REG;
550 rmh.cmd[1] = codec;
551 rmh.cmd[2] = (CS8420_DATA_FLOW_CTL & CHIP_SIG_AND_MAP_SPI) | (use_src ? 0x41 : 0x54);
552 err = pcxhr_send_msg(chip->mgr, &rmh);
555 rmh.cmd[2] = (CS8420_CLOCK_SRC_CTL & CHIP_SIG_AND_MAP_SPI) | (use_src ? 0x41 : 0x49);
556 err = pcxhr_send_msg(chip->mgr, &rmh);
740 struct pcxhr_rmh rmh;
742 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
743 rmh.cmd[0] |= IO_NUM_UER_CHIP_REG;
745 case 0: rmh.cmd[1] = CS8420_01_CS; break; /* use CS8416_01_CS for AES SYNC plug */
746 case 1: rmh.cmd[1] = CS8420_23_CS; break;
747 case 2: rmh.cmd[1] = CS8420_45_CS; break;
748 case 3: rmh.cmd[1] = CS8420_67_CS; break;
752 case 0: rmh.cmd[2] = CS8420_CSB0; break; /* use CS8416_CSBx for AES SYNC plug */
753 case 1: rmh.cmd[2] = CS8420_CSB1; break;
754 case 2: rmh.cmd[2] = CS8420_CSB2; break;
755 case 3: rmh.cmd[2] = CS8420_CSB3; break;
756 case 4: rmh.cmd[2] = CS8420_CSB4; break;
759 rmh.cmd[1] &= 0x0fffff; /* size and code the chip id for the fpga */
760 rmh.cmd[2] &= CHIP_SIG_AND_MAP_SPI; /* chip signature + map for spi read */
761 rmh.cmd_len = 3;
762 err = pcxhr_send_msg(chip->mgr, &rmh);
769 if (rmh.stat[1] & (1 << i))
812 struct pcxhr_rmh rmh;
822 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
823 rmh.cmd[0] |= IO_NUM_REG_CUER;
824 rmh.cmd[1] = cmd;
825 rmh.cmd_len = 2;
828 err = pcxhr_send_msg(chip->mgr, &rmh);