Lines Matching refs:SS_CSR
167 #define SS_CSR(t) (SER_BASE+t)
565 __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));
567 __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));
568 __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ));
569 __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ));
571 __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH));
572 __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH));
573 __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH));
578 SS_CSR(R_SER_LINE_MODE));
666 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))||
667 __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) {
684 SS_CSR(R_SER_DMA_CONFIG0_RX));
685 __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));
686 __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));
688 __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));
689 __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));
690 __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));
693 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
695 __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));
698 SS_CSR(R_SER_INT_MASK));
703 __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
705 __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
708 while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1)
713 (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff)));
754 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
920 status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0;
924 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
986 __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1042 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1067 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1606 while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) ||
1619 hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1792 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1855 __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
1992 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
2001 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2373 "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG))));
2399 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) {
2401 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)))
2501 status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG));
2508 status = __raw_readq(SS_CSR(R_SER_STATUS));
2520 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX)))
2522 newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2530 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));