Lines Matching refs:snd_opti9xx_write_mask
449 #define snd_opti9xx_write_mask(chip, reg, value, mask) \
465 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0xf0, 0xfc);
466 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6), 0x02, 0x02);
469 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), 0x80, 0x80);
470 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2), 0x00, 0x20);
471 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(3), 0xf0, 0xff);
473 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x02, 0x02);
475 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x00, 0x02);
481 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), 0x80, 0x80);
482 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2), 0x00, 0x20);
484 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(3), 0xa2, 0xae);
486 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0x00, 0x0c);
488 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x02, 0x02);
490 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x00, 0x02);
498 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6), 0x02, 0x03);
499 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(3), 0x00, 0xff);
500 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0x10 |
503 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x20, 0xbf);
529 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), wss_base_bits << 4, 0x30);
636 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6),
1821 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2),
1828 snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2),