Lines Matching refs:u32
20 #define MASK(msb, lsb) ( (((u32)1<<((msb)-(lsb)+1))-1) << (lsb) )
21 #define GET(v, msb, lsb) ( ((u32)(v) & MASK(msb,lsb)) >> (lsb) )
22 #define SET(v, f, msb, lsb) ( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) )
33 volatile u32 ctrlstat; /* 0x000000 general control */
34 volatile u32 dotclock; /* 0x000004 dot clock PLL control */
35 volatile u32 i2c; /* 0x000008 crt I2C control */
36 volatile u32 sysclk; /* 0x00000c system clock PLL control */
37 volatile u32 i2cfp; /* 0x000010 flat panel I2C control */
38 volatile u32 id; /* 0x000014 device id/chip revision */
39 volatile u32 config; /* 0x000018 power on configuration */
40 volatile u32 bist; /* 0x00001c internal bist status */
44 volatile u32 vt_xy; /* 0x010000 current dot coords */
45 volatile u32 vt_xymax; /* 0x010004 maximum dot coords */
46 volatile u32 vt_vsync; /* 0x010008 vsync on/off */
47 volatile u32 vt_hsync; /* 0x01000c hsync on/off */
48 volatile u32 vt_vblank; /* 0x010010 vblank on/off */
49 volatile u32 vt_hblank; /* 0x010014 hblank on/off */
50 volatile u32 vt_flags; /* 0x010018 polarity of vt signals */
51 volatile u32 vt_f2rf_lock; /* 0x01001c f2rf & framelck y coord */
52 volatile u32 vt_intr01; /* 0x010020 intr 0,1 y coords */
53 volatile u32 vt_intr23; /* 0x010024 intr 2,3 y coords */
54 volatile u32 fp_hdrv; /* 0x010028 flat panel hdrv on/off */
55 volatile u32 fp_vdrv; /* 0x01002c flat panel vdrv on/off */
56 volatile u32 fp_de; /* 0x010030 flat panel de on/off */
57 volatile u32 vt_hpixen; /* 0x010034 intrnl horiz pixel on/off*/
58 volatile u32 vt_vpixen; /* 0x010038 intrnl vert pixel on/off */
59 volatile u32 vt_hcmap; /* 0x01003c cmap write (horiz) */
60 volatile u32 vt_vcmap; /* 0x010040 cmap write (vert) */
61 volatile u32 did_start_xy; /* 0x010044 eol/f did/xy reset val */
62 volatile u32 crs_start_xy; /* 0x010048 eol/f crs/xy reset val */
63 volatile u32 vc_start_xy; /* 0x01004c eol/f vc/xy reset val */
67 volatile u32 ovr_width_tile; /* 0x020000 overlay plane ctrl 0 */
68 volatile u32 ovr_inhwctrl; /* 0x020004 overlay plane ctrl 1 */
69 volatile u32 ovr_control; /* 0x020008 overlay plane ctrl 1 */
73 volatile u32 frm_size_tile; /* 0x030000 normal plane ctrl 0 */
74 volatile u32 frm_size_pixel; /* 0x030004 normal plane ctrl 1 */
75 volatile u32 frm_inhwctrl; /* 0x030008 normal plane ctrl 2 */
76 volatile u32 frm_control; /* 0x03000C normal plane ctrl 3 */
80 volatile u32 did_inhwctrl; /* 0x040000 DID control */
81 volatile u32 did_control; /* 0x040004 DID shadow */
85 volatile u32 mode_regs[32]; /* 0x048000 - 0x04807c WID table */
89 volatile u32 cmap[6144]; /* 0x050000 - 0x055ffc color map */
93 volatile u32 cm_fifo; /* 0x058000 color map fifo status */
97 volatile u32 gmap[256]; /* 0x060000 - 0x0603fc gamma map */
101 volatile u32 gmap10[1024]; /* 0x068000 - 0x068ffc gamma map */
105 volatile u32 crs_pos; /* 0x070000 cusror control 0 */
106 volatile u32 crs_ctl; /* 0x070004 cusror control 1 */
107 volatile u32 crs_cmap[3]; /* 0x070008 - 0x070010 crs cmap */
111 volatile u32 crs_glyph[64]; /* 0x078000 - 0x0780fc crs glyph */
115 volatile u32 vc_0; /* 0x080000 video capture crtl 0 */
116 volatile u32 vc_1; /* 0x080004 video capture crtl 1 */
117 volatile u32 vc_2; /* 0x080008 video capture crtl 2 */
118 volatile u32 vc_3; /* 0x08000c video capture crtl 3 */
119 volatile u32 vc_4; /* 0x080010 video capture crtl 3 */
120 volatile u32 vc_5; /* 0x080014 video capture crtl 3 */
121 volatile u32 vc_6; /* 0x080018 video capture crtl 3 */
122 volatile u32 vc_7; /* 0x08001c video capture crtl 3 */
123 volatile u32 vc_8; /* 0x08000c video capture crtl 3 */