Lines Matching refs:zero
39 mtc0 zero, CP0_CAUSE
130 beq t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
133 ori t1, zero, 1
140 ori t2, zero, 1
153 move t0, zero
157 bne t2, zero, pr4450_next_instruction_cache_set
166 move t1, zero
169 mtc0 zero, CP0_TAGLO, 0
172 mtc0 zero, CP0_TAGHI, 0
176 or t2, zero, (128*4)-1 /* 512 lines */
181 bne t2, zero, 2b
195 mtc0 zero, CP0_STATUS /* disable CPU interrupts */
198 or t1, zero, zero /* T1 = starting cache index (0) */
199 ori t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */
209 bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
217 lw zero, 0x0000(t1) /* (dummy read of first memory word) */
229 mtc0 zero, CP0_STATUS /* disable CPU interrupts */
233 or t1, zero, zero /* T1 = starting cache index (0) */
234 ori t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */
248 bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
255 lw zero, 0x0000(t1) /* (dummy read of first memory word) */