Lines Matching refs:u32
30 u32 mbar; /* MMAP_CTRL + 0x00 */
32 u32 cs0_start; /* MMAP_CTRL + 0x04 */
33 u32 cs0_stop; /* MMAP_CTRL + 0x08 */
34 u32 cs1_start; /* MMAP_CTRL + 0x0c */
35 u32 cs1_stop; /* MMAP_CTRL + 0x10 */
36 u32 cs2_start; /* MMAP_CTRL + 0x14 */
37 u32 cs2_stop; /* MMAP_CTRL + 0x18 */
38 u32 cs3_start; /* MMAP_CTRL + 0x1c */
39 u32 cs3_stop; /* MMAP_CTRL + 0x20 */
40 u32 cs4_start; /* MMAP_CTRL + 0x24 */
41 u32 cs4_stop; /* MMAP_CTRL + 0x28 */
42 u32 cs5_start; /* MMAP_CTRL + 0x2c */
43 u32 cs5_stop; /* MMAP_CTRL + 0x30 */
45 u32 sdram0; /* MMAP_CTRL + 0x34 */
46 u32 sdram1; /* MMAP_CTRL + 0X38 */
48 u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
50 u32 boot_start; /* MMAP_CTRL + 0x4c */
51 u32 boot_stop; /* MMAP_CTRL + 0x50 */
53 u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
55 u32 cs6_start; /* MMAP_CTRL + 0x58 */
56 u32 cs6_stop; /* MMAP_CTRL + 0x5c */
57 u32 cs7_start; /* MMAP_CTRL + 0x60 */
58 u32 cs7_stop; /* MMAP_CTRL + 0x64 */
63 u32 mode; /* SDRAM + 0x00 */
64 u32 ctrl; /* SDRAM + 0x04 */
65 u32 config1; /* SDRAM + 0x08 */
66 u32 config2; /* SDRAM + 0x0c */
71 u32 taskBar; /* SDMA + 0x00 */
72 u32 currentPointer; /* SDMA + 0x04 */
73 u32 endPointer; /* SDMA + 0x08 */
74 u32 variablePointer; /* SDMA + 0x0c */
80 u32 IntPend; /* SDMA + 0x14 */
81 u32 IntMask; /* SDMA + 0x18 */
87 u32 cReqSelect; /* SDMA + 0x5c */
88 u32 task_size0; /* SDMA + 0x60 */
89 u32 task_size1; /* SDMA + 0x64 */
90 u32 MDEDebug; /* SDMA + 0x68 */
91 u32 ADSDebug; /* SDMA + 0x6c */
92 u32 Value1; /* SDMA + 0x70 */
93 u32 Value2; /* SDMA + 0x74 */
94 u32 Control; /* SDMA + 0x78 */
95 u32 Status; /* SDMA + 0x7c */
96 u32 PTDDebug; /* SDMA + 0x80 */
101 u32 mode; /* GPTx + 0x00 */
102 u32 count; /* GPTx + 0x04 */
103 u32 pwm; /* GPTx + 0x08 */
104 u32 status; /* GPTx + 0X0c */
109 u32 port_config; /* GPIO + 0x00 */
110 u32 simple_gpioe; /* GPIO + 0x04 */
111 u32 simple_ode; /* GPIO + 0x08 */
112 u32 simple_ddr; /* GPIO + 0x0c */
113 u32 simple_dvo; /* GPIO + 0x10 */
114 u32 simple_ival; /* GPIO + 0x14 */
170 u32 config; /* XLB + 0x40 */
171 u32 version; /* XLB + 0x44 */
172 u32 status; /* XLB + 0x48 */
173 u32 int_enable; /* XLB + 0x4c */
174 u32 addr_capture; /* XLB + 0x50 */
175 u32 bus_sig_capture; /* XLB + 0x54 */
176 u32 addr_timeout; /* XLB + 0x58 */
177 u32 data_timeout; /* XLB + 0x5c */
178 u32 bus_act_timeout; /* XLB + 0x60 */
179 u32 master_pri_enable; /* XLB + 0x64 */
180 u32 master_priority; /* XLB + 0x68 */
181 u32 base_address; /* XLB + 0x6c */
182 u32 snoop_window; /* XLB + 0x70 */
190 u32 jtag_id; /* CDM + 0x00 reg0 read only */
191 u32 rstcfg; /* CDM + 0x04 reg1 read only */
192 u32 breadcrumb; /* CDM + 0x08 reg2 */
203 u32 clk_enables; /* CDM + 0x14 reg5 */