Lines Matching refs:MMU_REG_BASE
57 #define MMU_REG_BASE (0xffff0000)
63 #define MATM MMU_REG_BASE /* MMU Address Translation Mode
65 #define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */
66 #define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */
67 #define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */
68 #define MDEVA (0x10 + MMU_REG_BASE) /* MMU Operand Exception Virtual
70 #define MDEVP (0x14 + MMU_REG_BASE) /* MMU Operand Exception Virtual Page
72 #define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */
73 #define MSVA (0x20 + MMU_REG_BASE) /* MMU Search Virtual Address
75 #define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */
76 #define MIDXI (0x28 + MMU_REG_BASE) /* MMU Index Register for
78 #define MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */
80 #define MATM_offset (MATM - MMU_REG_BASE)
81 #define MPSZ_offset (MPSZ - MMU_REG_BASE)
82 #define MASID_offset (MASID - MMU_REG_BASE)
83 #define MESTS_offset (MESTS - MMU_REG_BASE)
84 #define MDEVA_offset (MDEVA - MMU_REG_BASE)
85 #define MDEVP_offset (MDEVP - MMU_REG_BASE)
86 #define MPTB_offset (MPTB - MMU_REG_BASE)
87 #define MSVA_offset (MSVA - MMU_REG_BASE)
88 #define MTOP_offset (MTOP - MMU_REG_BASE)
89 #define MIDXI_offset (MIDXI - MMU_REG_BASE)
90 #define MIDXD_offset (MIDXD - MMU_REG_BASE)