Lines Matching defs:fbi
124 static void s3c2410fb_set_lcdaddr(struct s3c2410fb_info *fbi)
126 struct fb_var_screeninfo *var = &fbi->fb->var;
129 saddr1 = fbi->fb->fix.smem_start >> 1;
130 saddr2 = fbi->fb->fix.smem_start;
150 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
153 unsigned long clk = clk_get_rate(fbi->clk);
178 struct s3c2410fb_info *fbi = info->par;
184 if (var->yres > fbi->mach_info->yres.max)
185 var->yres = fbi->mach_info->yres.max;
186 else if (var->yres < fbi->mach_info->yres.min)
187 var->yres = fbi->mach_info->yres.min;
189 if (var->xres > fbi->mach_info->xres.max)
190 var->yres = fbi->mach_info->xres.max;
191 else if (var->xres < fbi->mach_info->xres.min)
192 var->xres = fbi->mach_info->xres.min;
196 if (var->bits_per_pixel > fbi->mach_info->bpp.max)
197 var->bits_per_pixel = fbi->mach_info->bpp.max;
198 else if (var->bits_per_pixel < fbi->mach_info->bpp.min)
199 var->bits_per_pixel = fbi->mach_info->bpp.min;
214 if ( fbi->mach_info->type != S3C2410_LCDCON1_TFT ) {
245 if (fbi->regs.lcdcon5 & S3C2410_LCDCON5_FRM565 ) {
288 static void s3c2410fb_activate_var(struct s3c2410fb_info *fbi,
293 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
294 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_TFT;
300 fbi->regs.lcdcon1 |= fbi->mach_info->type;
302 if (fbi->mach_info->type == S3C2410_LCDCON1_TFT)
305 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
308 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
311 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
314 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
317 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
322 dev_err(fbi->dev, "invalid bpp %d\n", var->bits_per_pixel);
327 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
330 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
333 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
336 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
339 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
344 dev_err(fbi->dev, "invalid bpp %d\n", var->bits_per_pixel);
349 if (!fbi->mach_info->fixed_syncs) {
358 fbi->regs.lcdcon2 =
363 fbi->regs.lcdcon3 =
367 fbi->regs.lcdcon4 &= ~S3C2410_LCDCON4_HSPW(0xff);
368 fbi->regs.lcdcon4 |= S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
373 fbi->regs.lcdcon2 &= ~S3C2410_LCDCON2_LINEVAL(0x3ff);
374 fbi->regs.lcdcon2 |= S3C2410_LCDCON2_LINEVAL(var->yres - 1);
376 switch(fbi->mach_info->type) {
392 if ( ((fbi->regs.lcdcon1 & S3C2410_LCDCON1_MODEMASK) == S3C2410_LCDCON1_STN8BPP) \
393 || ((fbi->regs.lcdcon1 & S3C2410_LCDCON1_MODEMASK) == S3C2410_LCDCON1_STN12BPP) ) {
398 fbi->regs.lcdcon3 &= ~S3C2410_LCDCON3_HOZVAL(0x7ff);
399 fbi->regs.lcdcon3 |= S3C2410_LCDCON3_HOZVAL(hs - 1);
402 int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
404 if (fbi->mach_info->type == S3C2410_LCDCON1_TFT) {
415 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
416 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
422 dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
423 dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
424 dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
425 dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
426 dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
428 writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID, S3C2410_LCDCON1);
429 writel(fbi->regs.lcdcon2, S3C2410_LCDCON2);
430 writel(fbi->regs.lcdcon3, S3C2410_LCDCON3);
431 writel(fbi->regs.lcdcon4, S3C2410_LCDCON4);
432 writel(fbi->regs.lcdcon5, S3C2410_LCDCON5);
435 s3c2410fb_set_lcdaddr(fbi);
437 writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
448 struct s3c2410fb_info *fbi = info->par;
454 fbi->fb->fix.visual = FB_VISUAL_TRUECOLOR;
457 fbi->fb->fix.visual = FB_VISUAL_MONO01;
460 fbi->fb->fix.visual = FB_VISUAL_PSEUDOCOLOR;
464 fbi->fb->fix.line_length = (var->width*var->bits_per_pixel)/8;
468 s3c2410fb_activate_var(fbi, var);
472 static void schedule_palette_update(struct s3c2410fb_info *fbi,
480 fbi->palette_buffer[regno] = val;
482 if (!fbi->palette_ready) {
483 fbi->palette_ready = 1;
506 struct s3c2410fb_info *fbi = info->par;
511 switch (fbi->fb->fix.visual) {
516 u32 *pal = fbi->fb->pseudo_palette;
518 val = chan_to_field(red, &fbi->fb->var.red);
519 val |= chan_to_field(green, &fbi->fb->var.green);
520 val |= chan_to_field(blue, &fbi->fb->var.blue);
535 schedule_palette_update(fbi, regno, val);
634 static int __init s3c2410fb_map_video_memory(struct s3c2410fb_info *fbi)
636 dprintk("map_video_memory(fbi=%p)\n", fbi);
638 fbi->map_size = PAGE_ALIGN(fbi->fb->fix.smem_len + PAGE_SIZE);
639 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
640 &fbi->map_dma, GFP_KERNEL);
642 fbi->map_size = fbi->fb->fix.smem_len;
644 if (fbi->map_cpu) {
647 fbi->map_cpu, fbi->map_size);
648 memset(fbi->map_cpu, 0xf0, fbi->map_size);
650 fbi->screen_dma = fbi->map_dma;
651 fbi->fb->screen_base = fbi->map_cpu;
652 fbi->fb->fix.smem_start = fbi->screen_dma;
655 fbi->map_dma, fbi->map_cpu, fbi->fb->fix.smem_len);
658 return fbi->map_cpu ? 0 : -ENOMEM;
661 static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info *fbi)
663 dma_free_writecombine(fbi->dev,fbi->map_size,fbi->map_cpu, fbi->map_dma);
680 static int s3c2410fb_init_registers(struct s3c2410fb_info *fbi)
697 writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
698 writel(fbi->regs.lcdcon2, S3C2410_LCDCON2);
699 writel(fbi->regs.lcdcon3, S3C2410_LCDCON3);
700 writel(fbi->regs.lcdcon4, S3C2410_LCDCON4);
701 writel(fbi->regs.lcdcon5, S3C2410_LCDCON5);
703 s3c2410fb_set_lcdaddr(fbi);
714 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
715 writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
719 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
724 fbi->palette_ready = 0;
727 if ((ent = fbi->palette_buffer[i]) == PALETTE_BUFF_CLEAR)
738 fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
740 fbi->palette_ready = 1; /* retry */
746 struct s3c2410fb_info *fbi = dev_id;
750 if (fbi->palette_ready)
751 s3c2410fb_write_palette(fbi);
931 static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi)
937 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
938 writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);