Lines Matching refs:dinfo
69 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
72 if (!pdev || !dinfo)
77 dinfo->name = "Intel(R) 830M";
78 dinfo->chipset = INTEL_830M;
79 dinfo->mobile = 1;
80 dinfo->pll_index = PLLS_I8xx;
83 dinfo->name = "Intel(R) 845G";
84 dinfo->chipset = INTEL_845G;
85 dinfo->mobile = 0;
86 dinfo->pll_index = PLLS_I8xx;
90 dinfo->mobile = 1;
91 dinfo->pll_index = PLLS_I8xx;
96 dinfo->name = "Intel(R) 855GME";
97 dinfo->chipset = INTEL_855GME;
100 dinfo->name = "Intel(R) 855GM";
101 dinfo->chipset = INTEL_855GM;
104 dinfo->name = "Intel(R) 852GME";
105 dinfo->chipset = INTEL_852GME;
108 dinfo->name = "Intel(R) 852GM";
109 dinfo->chipset = INTEL_852GM;
112 dinfo->name = "Intel(R) 852GM/855GM";
113 dinfo->chipset = INTEL_85XGM;
118 dinfo->name = "Intel(R) 865G";
119 dinfo->chipset = INTEL_865G;
120 dinfo->mobile = 0;
121 dinfo->pll_index = PLLS_I8xx;
124 dinfo->name = "Intel(R) 915G";
125 dinfo->chipset = INTEL_915G;
126 dinfo->mobile = 0;
127 dinfo->pll_index = PLLS_I9xx;
130 dinfo->name = "Intel(R) 915GM";
131 dinfo->chipset = INTEL_915GM;
132 dinfo->mobile = 1;
133 dinfo->pll_index = PLLS_I9xx;
136 dinfo->name = "Intel(R) 945G";
137 dinfo->chipset = INTEL_945G;
138 dinfo->mobile = 0;
139 dinfo->pll_index = PLLS_I9xx;
142 dinfo->name = "Intel(R) 945GM";
143 dinfo->chipset = INTEL_945GM;
144 dinfo->mobile = 1;
145 dinfo->pll_index = PLLS_I9xx;
258 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
291 intelfbhw_validate_mode(struct intelfb_info *dinfo,
307 if (tmp > dinfo->fb.size) {
310 BtoKB(tmp), BtoKB(dinfo->fb.size));
355 struct intelfb_info *dinfo = GET_DINFO(info);
369 offset = (yoffset * dinfo->pitch) +
372 offset += dinfo->fb.offset << 12;
374 dinfo->vsync.pan_offset = offset;
375 if ((var->activate & FB_ACTIVATE_VBL) && !intelfbhw_enable_irq(dinfo, 0)) {
376 dinfo->vsync.pan_display = 1;
378 dinfo->vsync.pan_display = 0;
389 struct intelfb_info *dinfo = GET_DINFO(info);
409 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
411 if (dinfo->cursor_on) {
413 intelfbhw_cursor_hide(dinfo);
415 intelfbhw_cursor_show(dinfo);
417 dinfo->cursor_on = 1;
419 dinfo->cursor_blanked = blank;
445 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
454 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
465 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
474 if (!hw || !dinfo)
625 intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, int *o_p1, int *o_p2)
629 if (IS_I9XX(dinfo)) {
653 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
657 int index = dinfo->pll_index;
671 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
682 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
698 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
708 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
976 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
1056 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1078 if (IS_I9XX(dinfo)) {
1189 hw->disp_a_stride = dinfo->pitch;
1195 hw->disp_a_base += dinfo->fb.offset << 12;
1198 stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1213 intelfbhw_program_mode(struct intelfb_info *dinfo,
1243 dinfo->pipe = pipe;
1380 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1412 static void refresh_ring(struct intelfb_info *dinfo);
1413 static void reset_state(struct intelfb_info *dinfo);
1414 static void do_flush(struct intelfb_info *dinfo);
1416 static u32 get_ring_space(struct intelfb_info *dinfo)
1420 if (dinfo->ring_tail >= dinfo->ring_head)
1421 ring_space = dinfo->ring.size -
1422 (dinfo->ring_tail - dinfo->ring_head);
1424 ring_space = dinfo->ring_head - dinfo->ring_tail;
1435 wait_ring(struct intelfb_info *dinfo, int n)
1446 while (dinfo->ring_space < n) {
1447 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1448 dinfo->ring_space = get_ring_space(dinfo);
1450 if (dinfo->ring_head != last_head) {
1452 last_head = dinfo->ring_head;
1458 reset_state(dinfo);
1459 refresh_ring(dinfo);
1460 do_flush(dinfo);
1465 dinfo->ring_space, n);
1468 dinfo->ring_lockup = 1;
1478 do_flush(struct intelfb_info *dinfo) {
1486 intelfbhw_do_sync(struct intelfb_info *dinfo)
1492 if (!dinfo->accel)
1500 do_flush(dinfo);
1501 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1502 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1506 refresh_ring(struct intelfb_info *dinfo)
1512 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1513 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1514 dinfo->ring_space = get_ring_space(dinfo);
1518 reset_state(struct intelfb_info *dinfo)
1536 refresh_ring(dinfo);
1537 intelfbhw_do_sync(dinfo);
1549 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1552 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1553 dinfo->ring_active);
1556 if (!dinfo->accel)
1559 dinfo->ring_active = 0;
1560 reset_state(dinfo);
1569 intelfbhw_2d_start(struct intelfb_info *dinfo)
1573 dinfo->accel, dinfo->ring_active);
1576 if (!dinfo->accel)
1584 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1586 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1588 refresh_ring(dinfo);
1589 dinfo->ring_active = 1;
1594 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1605 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1633 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1634 dinfo->ring_tail, dinfo->ring_space);
1639 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1650 br09 = dinfo->fb_start;
1652 br12 = dinfo->fb_start;
1685 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1721 br09 = dinfo->fb_start;
1774 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1782 if (dinfo->mobile || IS_I9XX(dinfo)) {
1783 if (!dinfo->cursor.physical)
1791 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1798 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1806 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1814 dinfo->cursor_on = 0;
1815 if (dinfo->mobile || IS_I9XX(dinfo)) {
1816 if (!dinfo->cursor.physical)
1823 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1832 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1840 dinfo->cursor_on = 1;
1842 if (dinfo->cursor_blanked)
1845 if (dinfo->mobile || IS_I9XX(dinfo)) {
1846 if (!dinfo->cursor.physical)
1853 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1862 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1880 if (IS_I9XX(dinfo)) {
1881 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1886 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1899 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1902 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1910 if (!dinfo->cursor.virtual)
1929 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1930 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1937 if (!dinfo->cursor.virtual)
1953 struct intelfb_info *dinfo = (struct intelfb_info *)dev_id;
1955 spin_lock(&dinfo->int_lock);
1961 spin_unlock(&dinfo->int_lock);
1968 dinfo->vsync.count++;
1969 if (dinfo->vsync.pan_display) {
1970 dinfo->vsync.pan_display = 0;
1971 OUTREG(DSPABASE, dinfo->vsync.pan_offset);
1973 wake_up_interruptible(&dinfo->vsync.wait);
1977 spin_unlock(&dinfo->int_lock);
1983 intelfbhw_enable_irq(struct intelfb_info *dinfo, int reenable) {
1985 if (!test_and_set_bit(0, &dinfo->irq_flags)) {
1986 if (request_irq(dinfo->pdev->irq, intelfbhw_irq, IRQF_SHARED,
1987 "intelfb", dinfo)) {
1988 clear_bit(0, &dinfo->irq_flags);
1992 spin_lock_irq(&dinfo->int_lock);
1996 spin_unlock_irq(&dinfo->int_lock);
2000 spin_lock_irq(&dinfo->int_lock);
2006 spin_unlock_irq(&dinfo->int_lock);
2012 intelfbhw_disable_irq(struct intelfb_info *dinfo) {
2015 if (test_and_clear_bit(0, &dinfo->irq_flags)) {
2016 if (dinfo->vsync.pan_display) {
2017 dinfo->vsync.pan_display = 0;
2018 OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2020 spin_lock_irq(&dinfo->int_lock);
2027 spin_unlock_irq(&dinfo->int_lock);
2029 free_irq(dinfo->pdev->irq, dinfo);
2034 intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe) {
2041 vsync = &dinfo->vsync;
2047 ret = intelfbhw_enable_irq(dinfo, 0);
2058 intelfbhw_enable_irq(dinfo, 1);