Lines Matching refs:ct
251 if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))
253 if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))
255 /*aty_calc_pll_ct(info, &pll->ct);*/
263 ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
265 if(pll->ct.xres > 0) {
267 ret /= pll->ct.xres;
287 pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl);
291 par->clk_wr_offset, pll->ct.vclk_fb_div,
292 pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real);
309 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
315 tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2);
322 tmp |= pll->ct.pll_ext_cntl;
327 aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par);
329 aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par);
332 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par);
335 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
336 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
354 aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par);
355 aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par);
380 pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;
382 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU;
383 pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
384 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
385 pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
387 pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par);
388 pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par);
391 pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
392 pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
406 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
407 pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07;
408 pll->ct.xclk_ref_div = 1;
409 switch (pll->ct.xclk_post_div) {
414 pll->ct.xclk_ref_div = 3;
415 pll->ct.xclk_post_div = 0;
419 printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div);
422 pll->ct.mclk_fb_mult = 2;
423 if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) {
424 pll->ct.mclk_fb_mult = 4;
425 pll->ct.xclk_post_div -= 1;
430 __FUNCTION__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div);
436 pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2;
437 pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2;
440 pll->ct.fifo_size = 32;
442 pll->ct.fifo_size = 24;
443 pll->ct.xclkpagefaultdelay += 2;
444 pll->ct.xclkmaxrasdelay += 3;
450 pll->ct.dsp_loop_latency = 10;
452 pll->ct.dsp_loop_latency = 8;
453 pll->ct.xclkpagefaultdelay += 2;
459 pll->ct.dsp_loop_latency = 9;
461 pll->ct.dsp_loop_latency = 8;
462 pll->ct.xclkpagefaultdelay += 1;
467 pll->ct.dsp_loop_latency = 11;
469 pll->ct.dsp_loop_latency = 10;
470 pll->ct.xclkpagefaultdelay += 1;
474 pll->ct.dsp_loop_latency = 8;
475 pll->ct.xclkpagefaultdelay += 3;
478 pll->ct.dsp_loop_latency = 11;
479 pll->ct.xclkpagefaultdelay += 3;
483 if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay)
484 pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1;
493 pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16;
498 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
500 pll->ct.xclk_post_div_real = postdividers[pll_ext_cntl & 0x07];
504 pll->ct.mclk_fb_div = mclk_fb_div;
508 pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
510 q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
511 (pll->ct.mclk_fb_mult * par->xclk_per);
521 pll->ct.xclk_post_div_real = postdividers[xpost_div];
522 pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8;
525 pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) /
526 (par->ref_clk_per * pll->ct.pll_ref_div);
528 __FUNCTION__, pllmclk, pllmclk / pll->ct.xclk_post_div_real);
532 pll->ct.pll_gen_cntl = OSC_EN;
534 pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */;
537 pll->ct.pll_ext_cntl = 0;
539 pll->ct.pll_ext_cntl = xpost_div;
541 if (pll->ct.mclk_fb_mult == 4)
542 pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B;
545 pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */
551 pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */
553 q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
563 pll->ct.sclk_fb_div = q * sclk_post_div_real / 8;
564 pll->ct.spll_cntl2 = mpost_div << 4;
566 pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) /
567 (par->ref_clk_per * pll->ct.pll_ref_div);
574 pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par);
575 pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC);
593 aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par);
594 aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par);
602 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
603 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
604 aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par);
605 aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par);
606 aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par);