Lines Matching refs:ep0state
452 dev->ep0state = EP0_IDLE;
956 switch (dev->ep0state) {
973 dev->ep0state = EP0_END_XFER;
988 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
1124 ep->dev->ep0state = EP0_STALL;
1492 dev->ep0state = EP0_IDLE;
1757 if (dev->ep0state == EP0_STALL
1792 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1798 switch (dev->ep0state) {
1874 dev->ep0state = EP0_IN_DATA_PHASE;
1876 dev->ep0state = EP0_OUT_DATA_PHASE;
1903 dev->ep0state = EP0_STALL;
1907 if (likely(dev->ep0state == EP0_IN_DATA_PHASE