Lines Matching defs:brg
114 u32 div, brg;
117 brg = mainclk_hz / speed_hz / (4 << div);
118 /* now we have BRG+1 in brg, so count with that */
119 if (brg < (4 + 1)) {
120 brg = (4 + 1); /* speed_hz too big */
121 break; /* set lowest brg (div is == 0) */
123 if (brg <= (63 + 1))
124 break; /* we have valid brg and div */
128 brg = (63 + 1); /* set highest brg and div */
130 brg--;
131 return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
700 /* use minimal allowed brg and div values as initial setting: */
878 * produce valid brg and div