Lines Matching refs:ctrl
185 static void start_int_poll_timer(struct controller *ctrl, int sec);
186 static int hpc_check_cmd_status(struct controller *ctrl);
188 static inline u8 shpc_readb(struct controller *ctrl, int reg)
190 return readb(ctrl->creg + reg);
193 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
195 writeb(val, ctrl->creg + reg);
198 static inline u16 shpc_readw(struct controller *ctrl, int reg)
200 return readw(ctrl->creg + reg);
203 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
205 writew(val, ctrl->creg + reg);
208 static inline u32 shpc_readl(struct controller *ctrl, int reg)
210 return readl(ctrl->creg + reg);
213 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
215 writel(val, ctrl->creg + reg);
218 static inline int shpc_indirect_read(struct controller *ctrl, int index,
222 u32 cap_offset = ctrl->cap_offset;
223 struct pci_dev *pdev = ctrl->pci_dev;
236 struct controller *ctrl = (struct controller *)data;
239 shpc_isr(0, ctrl);
241 init_timer(&ctrl->poll_timer);
245 start_int_poll_timer(ctrl, shpchp_poll_time);
251 static void start_int_poll_timer(struct controller *ctrl, int sec)
257 ctrl->poll_timer.function = &int_poll_timeout;
258 ctrl->poll_timer.data = (unsigned long)ctrl;
259 ctrl->poll_timer.expires = jiffies + sec * HZ;
260 add_timer(&ctrl->poll_timer);
263 static inline int is_ctrl_busy(struct controller *ctrl)
265 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
273 static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
277 if (!is_ctrl_busy(ctrl))
283 if (!is_ctrl_busy(ctrl))
290 static inline int shpc_wait_cmd(struct controller *ctrl)
297 rc = shpc_poll_ctrl_busy(ctrl);
299 rc = wait_event_interruptible_timeout(ctrl->queue,
300 !is_ctrl_busy(ctrl), timeout);
301 if (!rc && is_ctrl_busy(ctrl)) {
314 struct controller *ctrl = slot->ctrl;
319 mutex_lock(&slot->ctrl->cmd_lock);
321 if (!shpc_poll_ctrl_busy(ctrl)) {
336 shpc_writew(ctrl, CMD, temp_word);
341 retval = shpc_wait_cmd(slot->ctrl);
345 cmd_status = hpc_check_cmd_status(slot->ctrl);
352 mutex_unlock(&slot->ctrl->cmd_lock);
356 static int hpc_check_cmd_status(struct controller *ctrl)
359 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
387 struct controller *ctrl = slot->ctrl;
388 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
411 struct controller *ctrl = slot->ctrl;
412 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
436 struct controller *ctrl = slot->ctrl;
437 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
446 struct controller *ctrl = slot->ctrl;
447 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
457 struct controller *ctrl = slot->ctrl;
459 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
467 struct controller *ctrl = slot->ctrl;
468 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
519 struct controller *ctrl = slot->ctrl;
520 u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
521 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
535 struct controller *ctrl = slot->ctrl;
536 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
579 static void hpc_release_ctlr(struct controller *ctrl)
587 for (i = 0; i < ctrl->num_slots; i++) {
588 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
594 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
597 cleanup_slots(ctrl);
602 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
606 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
609 del_timer(&ctrl->poll_timer);
611 free_irq(ctrl->pci_dev->irq, ctrl);
612 pci_disable_msi(ctrl->pci_dev);
615 iounmap(ctrl->creg);
616 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
666 struct controller *ctrl = slot->ctrl;
669 pi = shpc_readb(ctrl, PROG_INTERFACE);
729 struct controller *ctrl = (struct controller *)dev_id;
734 intr_loc = shpc_readl(ctrl, INTR_LOC);
745 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
748 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
750 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
760 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
762 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
764 wake_up_interruptible(&ctrl->queue);
770 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
775 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
780 shpchp_handle_switch_change(hp_slot, ctrl);
783 shpchp_handle_attention_button(hp_slot, ctrl);
786 shpchp_handle_presence_change(hp_slot, ctrl);
789 shpchp_handle_power_fault(hp_slot, ctrl);
793 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
798 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
800 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
809 struct controller *ctrl = slot->ctrl;
811 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
812 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
813 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
854 struct controller *ctrl = slot->ctrl;
856 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
857 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
943 int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
951 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
956 ctrl->mmio_base = pci_resource_start(pdev, 0);
957 ctrl->mmio_size = pci_resource_len(pdev, 0);
959 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
960 if (!ctrl->cap_offset) {
964 dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);
966 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
972 rc = shpc_indirect_read(ctrl, 3, &tempdword);
981 rc = shpc_indirect_read(ctrl, i, &tempdword);
991 ctrl->mmio_base =
993 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
1005 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
1011 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1012 if (!ctrl->creg) {
1014 ctrl->mmio_size, ctrl->mmio_base);
1015 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1019 dbg("%s: ctrl->creg %p\n", __FUNCTION__, ctrl->creg);
1021 mutex_init(&ctrl->crit_sect);
1022 mutex_init(&ctrl->cmd_lock);
1025 init_waitqueue_head(&ctrl->queue);
1027 ctrl->hpc_ops = &shpchp_hpc_ops;
1030 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1031 ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1032 ctrl->num_slots = slot_config & SLOT_NUM;
1033 ctrl->first_slot = (slot_config & PSN) >> 16;
1034 ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
1037 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1042 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1043 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1049 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1050 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1058 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1063 init_timer(&ctrl->poll_timer);
1064 start_int_poll_timer(ctrl, 10);
1073 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
1074 MY_NAME, (void *)ctrl);
1076 __FUNCTION__, ctrl->pci_dev->irq,
1080 ctrl->pci_dev->irq);
1104 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1105 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1111 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1115 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1118 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1119 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1127 iounmap(ctrl->creg);