Lines Matching refs:ctrl
74 struct controller *ctrl;
158 extern int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
159 extern void shpchp_remove_ctrl_files(struct controller *ctrl);
162 extern u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
163 extern u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
164 extern u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
165 extern u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
168 extern void cleanup_slots(struct controller *ctrl);
170 extern int shpc_init( struct controller *ctrl, struct pci_dev *pdev);
228 static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
232 list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
246 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
248 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
256 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
268 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
273 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
277 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
282 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
285 pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
287 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
292 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
297 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
302 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
307 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
311 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
333 void (*release_ctlr)(struct controller *ctrl);
334 int (*check_cmd_status)(struct controller *ctrl);