Lines Matching refs:ctlr
90 #define WPG_1ST_SLOT_INDEX 0x01 // index - 1st slot for ctlr
91 #define WPG_CTLR_INDEX 0x0F // index - ctlr
92 #define WPG_1ST_EXTSLOT_INDEX 0x10 // index - 1st ext slot for ctlr
93 #define WPG_1ST_BUS_INDEX 0x1F // index - 1st bus for ctlr
404 static u8 ctrl_read (struct controller *ctlr, void __iomem *base, u8 offset)
407 switch (ctlr->ctlr_type) {
409 rc = isa_ctrl_read (ctlr, offset);
412 rc = pci_ctrl_read (ctlr, offset);
416 rc = i2c_ctrl_read (ctlr, base, offset);
424 static u8 ctrl_write (struct controller *ctlr, void __iomem *base, u8 offset, u8 data)
427 switch (ctlr->ctlr_type) {
429 isa_ctrl_write(ctlr, offset, data);
432 rc = pci_ctrl_write (ctlr, offset, data);
436 rc = i2c_ctrl_write(ctlr, base, offset, data);
726 debug ("%s - ctlr id[%x] physical[%lx] logical[%lx] i2c[%x]\n", __FUNCTION__,
1155 err ("HPCreadslot - Error ctlr timeout\n");