Lines Matching refs:bcm
81 static void bcm43xx_phy_initg(struct bcm43xx_private *bcm);
94 void bcm43xx_raw_phy_lock(struct bcm43xx_private *bcm)
96 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
99 if (bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD) == 0x00000000) {
103 if (bcm->current_core->rev < 3) {
104 bcm43xx_mac_suspend(bcm);
107 if (bcm->ieee->iw_mode != IW_MODE_MASTER)
108 bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
113 void bcm43xx_raw_phy_unlock(struct bcm43xx_private *bcm)
115 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
118 if (bcm->current_core->rev < 3) {
121 bcm43xx_mac_enable(bcm);
124 if (bcm->ieee->iw_mode != IW_MODE_MASTER)
125 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
130 u16 bcm43xx_phy_read(struct bcm43xx_private *bcm, u16 offset)
132 bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_CONTROL, offset);
133 return bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_DATA);
136 void bcm43xx_phy_write(struct bcm43xx_private *bcm, u16 offset, u16 val)
138 bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_CONTROL, offset);
140 bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_DATA, val);
143 void bcm43xx_phy_calibrate(struct bcm43xx_private *bcm)
145 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
147 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* Dummy read. */
151 bcm43xx_wireless_core_reset(bcm, 0);
152 bcm43xx_phy_initg(bcm);
153 bcm43xx_wireless_core_reset(bcm, 1);
159 * http://bcm-specs.sipsolutions.net/SetPHY
161 int bcm43xx_phy_connect(struct bcm43xx_private *bcm, int connect)
163 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
166 if (bcm->current_core->rev < 5)
169 flags = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
173 flags = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
175 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, flags);
179 flags = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
181 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, flags);
194 * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
196 static void bcm43xx_phy_init_pctl(struct bcm43xx_private *bcm)
198 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
199 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
204 if ((bcm->board_vendor == PCI_VENDOR_ID_BROADCOM) &&
205 (bcm->board_type == 0x0416))
208 bcm43xx_phy_write(bcm, 0x0028, 0x8018);
209 bcm43xx_write16(bcm, 0x03E6, bcm43xx_read16(bcm, 0x03E6) & 0xFFDF);
214 bcm43xx_phy_write(bcm, 0x047A, 0xC111);
222 bcm43xx_radio_write16(bcm, 0x0076,
223 bcm43xx_radio_read16(bcm, 0x0076) | 0x0084);
230 bcm43xx_radio_set_txpower_bg(bcm, 0xB, 0x1F, 0);
232 bcm43xx_radio_set_txpower_bg(bcm, 0xB, 9, 0);
235 bcm43xx_dummy_transmission(bcm);
237 phy->savedpctlreg = bcm43xx_phy_read(bcm, BCM43xx_PHY_G_PCTL);
240 bcm43xx_radio_set_txpower_bg(bcm, saved_batt, saved_ratt, saved_txctl1);
242 bcm43xx_radio_write16(bcm, 0x0076, bcm43xx_radio_read16(bcm, 0x0076) & 0xFF7B);
243 bcm43xx_radio_clear_tssi(bcm);
246 static void bcm43xx_phy_agcsetup(struct bcm43xx_private *bcm)
248 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
254 bcm43xx_ilt_write(bcm, offset, 0x00FE);
255 bcm43xx_ilt_write(bcm, offset + 1, 0x000D);
256 bcm43xx_ilt_write(bcm, offset + 2, 0x0013);
257 bcm43xx_ilt_write(bcm, offset + 3, 0x0019);
260 bcm43xx_ilt_write(bcm, 0x1800, 0x2710);
261 bcm43xx_ilt_write(bcm, 0x1801, 0x9B83);
262 bcm43xx_ilt_write(bcm, 0x1802, 0x9B83);
263 bcm43xx_ilt_write(bcm, 0x1803, 0x0F8D);
264 bcm43xx_phy_write(bcm, 0x0455, 0x0004);
267 bcm43xx_phy_write(bcm, 0x04A5, (bcm43xx_phy_read(bcm, 0x04A5) & 0x00FF) | 0x5700);
268 bcm43xx_phy_write(bcm, 0x041A, (bcm43xx_phy_read(bcm, 0x041A) & 0xFF80) | 0x000F);
269 bcm43xx_phy_write(bcm, 0x041A, (bcm43xx_phy_read(bcm, 0x041A) & 0xC07F) | 0x2B80);
270 bcm43xx_phy_write(bcm, 0x048C, (bcm43xx_phy_read(bcm, 0x048C) & 0xF0FF) | 0x0300);
272 bcm43xx_radio_write16(bcm, 0x007A, bcm43xx_radio_read16(bcm, 0x007A) | 0x0008);
274 bcm43xx_phy_write(bcm, 0x04A0, (bcm43xx_phy_read(bcm, 0x04A0) & 0xFFF0) | 0x0008);
275 bcm43xx_phy_write(bcm, 0x04A1, (bcm43xx_phy_read(bcm, 0x04A1) & 0xF0FF) | 0x0600);
276 bcm43xx_phy_write(bcm, 0x04A2, (bcm43xx_phy_read(bcm, 0x04A2) & 0xF0FF) | 0x0700);
277 bcm43xx_phy_write(bcm, 0x04A0, (bcm43xx_phy_read(bcm, 0x04A0) & 0xF0FF) | 0x0100);
280 bcm43xx_phy_write(bcm, 0x04A2, (bcm43xx_phy_read(bcm, 0x04A2) & 0xFFF0) | 0x0007);
282 bcm43xx_phy_write(bcm, 0x0488, (bcm43xx_phy_read(bcm, 0x0488) & 0xFF00) | 0x001C);
283 bcm43xx_phy_write(bcm, 0x0488, (bcm43xx_phy_read(bcm, 0x0488) & 0xC0FF) | 0x0200);
284 bcm43xx_phy_write(bcm, 0x0496, (bcm43xx_phy_read(bcm, 0x0496) & 0xFF00) | 0x001C);
285 bcm43xx_phy_write(bcm, 0x0489, (bcm43xx_phy_read(bcm, 0x0489) & 0xFF00) | 0x0020);
286 bcm43xx_phy_write(bcm, 0x0489, (bcm43xx_phy_read(bcm, 0x0489) & 0xC0FF) | 0x0200);
287 bcm43xx_phy_write(bcm, 0x0482, (bcm43xx_phy_read(bcm, 0x0482) & 0xFF00) | 0x002E);
288 bcm43xx_phy_write(bcm, 0x0496, (bcm43xx_phy_read(bcm, 0x0496) & 0x00FF) | 0x1A00);
289 bcm43xx_phy_write(bcm, 0x0481, (bcm43xx_phy_read(bcm, 0x0481) & 0xFF00) | 0x0028);
290 bcm43xx_phy_write(bcm, 0x0481, (bcm43xx_phy_read(bcm, 0x0481) & 0x00FF) | 0x2C00);
293 bcm43xx_phy_write(bcm, 0x0430, 0x092B);
294 bcm43xx_phy_write(bcm, 0x041B, (bcm43xx_phy_read(bcm, 0x041B) & 0xFFE1) | 0x0002);
296 bcm43xx_phy_write(bcm, 0x041B, bcm43xx_phy_read(bcm, 0x041B) & 0xFFE1);
297 bcm43xx_phy_write(bcm, 0x041F, 0x287A);
298 bcm43xx_phy_write(bcm, 0x0420, (bcm43xx_phy_read(bcm, 0x0420) & 0xFFF0) | 0x0004);
302 bcm43xx_phy_write(bcm, 0x0422, 0x287A);
303 bcm43xx_phy_write(bcm, 0x0420, (bcm43xx_phy_read(bcm, 0x0420)
307 bcm43xx_phy_write(bcm, 0x04A8, (bcm43xx_phy_read(bcm, 0x04A8) & 0x8080)
309 bcm43xx_phy_write(bcm, 0x048E, 0x1C00);
312 bcm43xx_phy_write(bcm, 0x04AB, (bcm43xx_phy_read(bcm, 0x04AB)
314 bcm43xx_phy_write(bcm, 0x048B, 0x005E);
315 bcm43xx_phy_write(bcm, 0x048C, (bcm43xx_phy_read(bcm, 0x048C)
317 bcm43xx_phy_write(bcm, 0x048D, 0x0002);
320 bcm43xx_ilt_write(bcm, offset + 0x0800, 0);
321 bcm43xx_ilt_write(bcm, offset + 0x0801, 7);
322 bcm43xx_ilt_write(bcm, offset + 0x0802, 16);
323 bcm43xx_ilt_write(bcm, offset + 0x0803, 28);
326 bcm43xx_phy_write(bcm, 0x0426, (bcm43xx_phy_read(bcm, 0x0426)
328 bcm43xx_phy_write(bcm, 0x0426, (bcm43xx_phy_read(bcm, 0x0426)
333 static void bcm43xx_phy_setupg(struct bcm43xx_private *bcm)
335 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
340 bcm43xx_phy_write(bcm, 0x0406, 0x4F19);
341 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
342 (bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS)
344 bcm43xx_phy_write(bcm, 0x042C, 0x005A);
345 bcm43xx_phy_write(bcm, 0x0427, 0x001A);
348 bcm43xx_ilt_write(bcm, 0x5800 + i, bcm43xx_ilt_finefreqg[i]);
350 bcm43xx_ilt_write(bcm, 0x1800 + i, bcm43xx_ilt_noiseg1[i]);
352 bcm43xx_ilt_write32(bcm, 0x2000 + i, bcm43xx_ilt_rotor[i]);
355 bcm43xx_nrssi_hw_write(bcm, 0xBA98, (s16)0x7654);
358 bcm43xx_phy_write(bcm, 0x04C0, 0x1861);
359 bcm43xx_phy_write(bcm, 0x04C1, 0x0271);
361 bcm43xx_phy_write(bcm, 0x04C0, 0x0098);
362 bcm43xx_phy_write(bcm, 0x04C1, 0x0070);
363 bcm43xx_phy_write(bcm, 0x04C9, 0x0080);
365 bcm43xx_phy_write(bcm, 0x042B, bcm43xx_phy_read(bcm, 0x042B) | 0x800);
368 bcm43xx_ilt_write(bcm, 0x4000 + i, i);
370 bcm43xx_ilt_write(bcm, 0x1800 + i, bcm43xx_ilt_noiseg2[i]);
375 bcm43xx_ilt_write(bcm, 0x1400 + i, bcm43xx_ilt_noisescaleg1[i]);
376 else if ((phy->rev >= 7) && (bcm43xx_phy_read(bcm, 0x0449) & 0x0200))
378 bcm43xx_ilt_write(bcm, 0x1400 + i, bcm43xx_ilt_noisescaleg3[i]);
381 bcm43xx_ilt_write(bcm, 0x1400 + i, bcm43xx_ilt_noisescaleg2[i]);
385 bcm43xx_ilt_write(bcm, 0x5000 + i, bcm43xx_ilt_sigmasqr1[i]);
388 bcm43xx_ilt_write(bcm, 0x5000 + i, bcm43xx_ilt_sigmasqr2[i]);
392 bcm43xx_ilt_write32(bcm, 0x2400 + i, bcm43xx_ilt_retard[i]);
394 bcm43xx_ilt_write(bcm, 0x5404 + i, 0x0020);
395 bcm43xx_ilt_write(bcm, 0x5408 + i, 0x0020);
396 bcm43xx_ilt_write(bcm, 0x540C + i, 0x0020);
397 bcm43xx_ilt_write(bcm, 0x5410 + i, 0x0020);
399 bcm43xx_phy_agcsetup(bcm);
401 if ((bcm->board_vendor == PCI_VENDOR_ID_BROADCOM) &&
402 (bcm->board_type == 0x0416) &&
403 (bcm->board_revision == 0x0017))
406 bcm43xx_ilt_write(bcm, 0x5001, 0x0002);
407 bcm43xx_ilt_write(bcm, 0x5002, 0x0001);
410 bcm43xx_ilt_write(bcm, 0x1000 + i, 0x0820);
411 bcm43xx_phy_agcsetup(bcm);
412 bcm43xx_phy_read(bcm, 0x0400); /* dummy read */
413 bcm43xx_phy_write(bcm, 0x0403, 0x1000);
414 bcm43xx_ilt_write(bcm, 0x3C02, 0x000F);
415 bcm43xx_ilt_write(bcm, 0x3C03, 0x0014);
417 if ((bcm->board_vendor == PCI_VENDOR_ID_BROADCOM) &&
418 (bcm->board_type == 0x0416) &&
419 (bcm->board_revision == 0x0017))
422 bcm43xx_ilt_write(bcm, 0x0401, 0x0002);
423 bcm43xx_ilt_write(bcm, 0x0402, 0x0001);
428 static void bcm43xx_phy_init_noisescaletbl(struct bcm43xx_private *bcm)
430 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
433 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_CTRL, 0x1400);
436 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x6767);
438 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x2323);
441 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x6700);
443 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x2300);
446 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x6767);
448 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x2323);
451 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x0067);
453 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x0023);
456 static void bcm43xx_phy_setupa(struct bcm43xx_private *bcm)
458 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
464 bcm43xx_phy_write(bcm, 0x008E, 0x3800);
465 bcm43xx_phy_write(bcm, 0x0035, 0x03FF);
466 bcm43xx_phy_write(bcm, 0x0036, 0x0400);
468 bcm43xx_ilt_write(bcm, 0x3807, 0x0051);
470 bcm43xx_phy_write(bcm, 0x001C, 0x0FF9);
471 bcm43xx_phy_write(bcm, 0x0020, bcm43xx_phy_read(bcm, 0x0020) & 0xFF0F);
472 bcm43xx_ilt_write(bcm, 0x3C0C, 0x07BF);
473 bcm43xx_radio_write16(bcm, 0x0002, 0x07BF);
475 bcm43xx_phy_write(bcm, 0x0024, 0x4680);
476 bcm43xx_phy_write(bcm, 0x0020, 0x0003);
477 bcm43xx_phy_write(bcm, 0x001D, 0x0F40);
478 bcm43xx_phy_write(bcm, 0x001F, 0x1C00);
480 bcm43xx_phy_write(bcm, 0x002A, (bcm43xx_phy_read(bcm, 0x002A) & 0x00FF) | 0x0400);
481 bcm43xx_phy_write(bcm, 0x002B, bcm43xx_phy_read(bcm, 0x002B) & 0xFBFF);
482 bcm43xx_phy_write(bcm, 0x008E, 0x58C1);
484 bcm43xx_ilt_write(bcm, 0x0803, 0x000F);
485 bcm43xx_ilt_write(bcm, 0x0804, 0x001F);
486 bcm43xx_ilt_write(bcm, 0x0805, 0x002A);
487 bcm43xx_ilt_write(bcm, 0x0805, 0x0030);
488 bcm43xx_ilt_write(bcm, 0x0807, 0x003A);
490 bcm43xx_ilt_write(bcm, 0x0000, 0x0013);
491 bcm43xx_ilt_write(bcm, 0x0001, 0x0013);
492 bcm43xx_ilt_write(bcm, 0x0002, 0x0013);
493 bcm43xx_ilt_write(bcm, 0x0003, 0x0013);
494 bcm43xx_ilt_write(bcm, 0x0004, 0x0015);
495 bcm43xx_ilt_write(bcm, 0x0005, 0x0015);
496 bcm43xx_ilt_write(bcm, 0x0006, 0x0019);
498 bcm43xx_ilt_write(bcm, 0x0404, 0x0003);
499 bcm43xx_ilt_write(bcm, 0x0405, 0x0003);
500 bcm43xx_ilt_write(bcm, 0x0406, 0x0007);
503 bcm43xx_ilt_write(bcm, 0x4000 + i, (0x8 + i) & 0x000F);
505 bcm43xx_ilt_write(bcm, 0x3003, 0x1044);
506 bcm43xx_ilt_write(bcm, 0x3004, 0x7201);
507 bcm43xx_ilt_write(bcm, 0x3006, 0x0040);
508 bcm43xx_ilt_write(bcm, 0x3001, (bcm43xx_ilt_read(bcm, 0x3001) & 0x0010) | 0x0008);
511 bcm43xx_ilt_write(bcm, 0x5800 + i, bcm43xx_ilt_finefreqa[i]);
513 bcm43xx_ilt_write(bcm, 0x1800 + i, bcm43xx_ilt_noisea2[i]);
515 bcm43xx_ilt_write32(bcm, 0x2000 + i, bcm43xx_ilt_rotor[i]);
516 bcm43xx_phy_init_noisescaletbl(bcm);
518 bcm43xx_ilt_write32(bcm, 0x2400 + i, bcm43xx_ilt_retard[i]);
522 bcm43xx_ilt_write(bcm, 0x4000 + i, i);
524 bcm43xx_ilt_write(bcm, 0x3807, 0x0051);
526 bcm43xx_phy_write(bcm, 0x001C, 0x0FF9);
527 bcm43xx_phy_write(bcm, 0x0020, bcm43xx_phy_read(bcm, 0x0020) & 0xFF0F);
528 bcm43xx_radio_write16(bcm, 0x0002, 0x07BF);
530 bcm43xx_phy_write(bcm, 0x0024, 0x4680);
531 bcm43xx_phy_write(bcm, 0x0020, 0x0003);
532 bcm43xx_phy_write(bcm, 0x001D, 0x0F40);
533 bcm43xx_phy_write(bcm, 0x001F, 0x1C00);
534 bcm43xx_phy_write(bcm, 0x002A, (bcm43xx_phy_read(bcm, 0x002A) & 0x00FF) | 0x0400);
536 bcm43xx_ilt_write(bcm, 0x3001, (bcm43xx_ilt_read(bcm, 0x3001) & 0x0010) | 0x0008);
538 bcm43xx_ilt_write(bcm, 0x1800 + i, bcm43xx_ilt_noisea3[i]);
539 bcm43xx_phy_init_noisescaletbl(bcm);
541 bcm43xx_ilt_write(bcm, 0x5000 + i, bcm43xx_ilt_sigmasqr1[i]);
543 bcm43xx_phy_write(bcm, 0x0003, 0x1808);
545 bcm43xx_ilt_write(bcm, 0x0803, 0x000F);
546 bcm43xx_ilt_write(bcm, 0x0804, 0x001F);
547 bcm43xx_ilt_write(bcm, 0x0805, 0x002A);
548 bcm43xx_ilt_write(bcm, 0x0805, 0x0030);
549 bcm43xx_ilt_write(bcm, 0x0807, 0x003A);
551 bcm43xx_ilt_write(bcm, 0x0000, 0x0013);
552 bcm43xx_ilt_write(bcm, 0x0001, 0x0013);
553 bcm43xx_ilt_write(bcm, 0x0002, 0x0013);
554 bcm43xx_ilt_write(bcm, 0x0003, 0x0013);
555 bcm43xx_ilt_write(bcm, 0x0004, 0x0015);
556 bcm43xx_ilt_write(bcm, 0x0005, 0x0015);
557 bcm43xx_ilt_write(bcm, 0x0006, 0x0019);
559 bcm43xx_ilt_write(bcm, 0x0404, 0x0003);
560 bcm43xx_ilt_write(bcm, 0x0405, 0x0003);
561 bcm43xx_ilt_write(bcm, 0x0406, 0x0007);
563 bcm43xx_ilt_write(bcm, 0x3C02, 0x000F);
564 bcm43xx_ilt_write(bcm, 0x3C03, 0x0014);
572 static void bcm43xx_phy_inita(struct bcm43xx_private *bcm)
574 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
575 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
579 bcm43xx_phy_setupa(bcm);
581 bcm43xx_phy_setupg(bcm);
582 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
583 bcm43xx_phy_write(bcm, 0x046E, 0x03CF);
587 bcm43xx_phy_write(bcm, BCM43xx_PHY_A_CRS,
588 (bcm43xx_phy_read(bcm, BCM43xx_PHY_A_CRS) & 0xF83C) | 0x0340);
589 bcm43xx_phy_write(bcm, 0x0034, 0x0001);
592 bcm43xx_phy_write(bcm, BCM43xx_PHY_A_CRS,
593 bcm43xx_phy_read(bcm, BCM43xx_PHY_A_CRS) | (1 << 14));
594 bcm43xx_radio_init2060(bcm);
596 if ((bcm->board_vendor == PCI_VENDOR_ID_BROADCOM)
597 && ((bcm->board_type == 0x0416) || (bcm->board_type == 0x040A))) {
600 bcm43xx_radio_set_tx_iq(bcm);
602 bcm43xx_radio_write16(bcm, 0x001E, radio->lofcal);
605 bcm43xx_phy_write(bcm, 0x007A, 0xF111);
608 bcm43xx_radio_write16(bcm, 0x0019, 0x0000);
609 bcm43xx_radio_write16(bcm, 0x0017, 0x0020);
611 tval = bcm43xx_ilt_read(bcm, 0x3001);
613 bcm43xx_ilt_write(bcm, 0x3001,
614 (bcm43xx_ilt_read(bcm, 0x3001) & 0xFF87)
617 bcm43xx_ilt_write(bcm, 0x3001,
618 (bcm43xx_ilt_read(bcm, 0x3001) & 0xFFC3)
621 bcm43xx_dummy_transmission(bcm);
622 phy->savedpctlreg = bcm43xx_phy_read(bcm, BCM43xx_PHY_A_PCTL);
623 bcm43xx_ilt_write(bcm, 0x3001, tval);
625 bcm43xx_radio_set_txpower_a(bcm, 0x0018);
627 bcm43xx_radio_clear_tssi(bcm);
630 static void bcm43xx_phy_initb2(struct bcm43xx_private *bcm)
632 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
635 bcm43xx_write16(bcm, 0x03EC, 0x3F22);
636 bcm43xx_phy_write(bcm, 0x0020, 0x301C);
637 bcm43xx_phy_write(bcm, 0x0026, 0x0000);
638 bcm43xx_phy_write(bcm, 0x0030, 0x00C6);
639 bcm43xx_phy_write(bcm, 0x0088, 0x3E00);
642 bcm43xx_phy_write(bcm, offset, val);
645 bcm43xx_phy_write(bcm, 0x03E4, 0x3000);
647 bcm43xx_radio_selectchannel(bcm, BCM43xx_RADIO_DEFAULT_CHANNEL_BG, 0);
649 bcm43xx_radio_selectchannel(bcm, radio->channel, 0);
651 bcm43xx_radio_write16(bcm, 0x0075, 0x0080);
652 bcm43xx_radio_write16(bcm, 0x0079, 0x0081);
654 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
655 bcm43xx_radio_write16(bcm, 0x0050, 0x0023);
657 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
658 bcm43xx_radio_write16(bcm, 0x005A, 0x0070);
659 bcm43xx_radio_write16(bcm, 0x005B, 0x007B);
660 bcm43xx_radio_write16(bcm, 0x005C, 0x00B0);
661 bcm43xx_radio_write16(bcm, 0x007A, 0x000F);
662 bcm43xx_phy_write(bcm, 0x0038, 0x0677);
663 bcm43xx_radio_init2050(bcm);
665 bcm43xx_phy_write(bcm, 0x0014, 0x0080);
666 bcm43xx_phy_write(bcm, 0x0032, 0x00CA);
667 bcm43xx_phy_write(bcm, 0x0032, 0x00CC);
668 bcm43xx_phy_write(bcm, 0x0035, 0x07C2);
669 bcm43xx_phy_lo_b_measure(bcm);
670 bcm43xx_phy_write(bcm, 0x0026, 0xCC00);
672 bcm43xx_phy_write(bcm, 0x0026, 0xCE00);
673 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT, 0x1000);
674 bcm43xx_phy_write(bcm, 0x002A, 0x88A3);
676 bcm43xx_phy_write(bcm, 0x002A, 0x88C2);
677 bcm43xx_radio_set_txpower_bg(bcm, 0xFFFF, 0xFFFF, 0xFFFF);
678 bcm43xx_phy_init_pctl(bcm);
681 static void bcm43xx_phy_initb4(struct bcm43xx_private *bcm)
683 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
686 bcm43xx_write16(bcm, 0x03EC, 0x3F22);
687 bcm43xx_phy_write(bcm, 0x0020, 0x301C);
688 bcm43xx_phy_write(bcm, 0x0026, 0x0000);
689 bcm43xx_phy_write(bcm, 0x0030, 0x00C6);
690 bcm43xx_phy_write(bcm, 0x0088, 0x3E00);
693 bcm43xx_phy_write(bcm, offset, val);
696 bcm43xx_phy_write(bcm, 0x03E4, 0x3000);
698 bcm43xx_radio_selectchannel(bcm, BCM43xx_RADIO_DEFAULT_CHANNEL_BG, 0);
700 bcm43xx_radio_selectchannel(bcm, radio->channel, 0);
702 bcm43xx_radio_write16(bcm, 0x0075, 0x0080);
703 bcm43xx_radio_write16(bcm, 0x0079, 0x0081);
705 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
706 bcm43xx_radio_write16(bcm, 0x0050, 0x0023);
708 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
709 bcm43xx_radio_write16(bcm, 0x005A, 0x0070);
710 bcm43xx_radio_write16(bcm, 0x005B, 0x007B);
711 bcm43xx_radio_write16(bcm, 0x005C, 0x00B0);
712 bcm43xx_radio_write16(bcm, 0x007A, 0x000F);
713 bcm43xx_phy_write(bcm, 0x0038, 0x0677);
714 bcm43xx_radio_init2050(bcm);
716 bcm43xx_phy_write(bcm, 0x0014, 0x0080);
717 bcm43xx_phy_write(bcm, 0x0032, 0x00CA);
719 bcm43xx_phy_write(bcm, 0x0032, 0x00E0);
720 bcm43xx_phy_write(bcm, 0x0035, 0x07C2);
722 bcm43xx_phy_lo_b_measure(bcm);
724 bcm43xx_phy_write(bcm, 0x0026, 0xCC00);
726 bcm43xx_phy_write(bcm, 0x0026, 0xCE00);
727 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT, 0x1100);
728 bcm43xx_phy_write(bcm, 0x002A, 0x88A3);
730 bcm43xx_phy_write(bcm, 0x002A, 0x88C2);
731 bcm43xx_radio_set_txpower_bg(bcm, 0xFFFF, 0xFFFF, 0xFFFF);
732 if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
733 bcm43xx_calc_nrssi_slope(bcm);
734 bcm43xx_calc_nrssi_threshold(bcm);
736 bcm43xx_phy_init_pctl(bcm);
739 static void bcm43xx_phy_initb5(struct bcm43xx_private *bcm)
741 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
742 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
748 bcm43xx_radio_write16(bcm, 0x007A,
749 bcm43xx_radio_read16(bcm, 0x007A)
751 if ((bcm->board_vendor != PCI_VENDOR_ID_BROADCOM) &&
752 (bcm->board_type != 0x0416)) {
755 bcm43xx_phy_write(bcm, offset, value);
759 bcm43xx_phy_write(bcm, 0x0035,
760 (bcm43xx_phy_read(bcm, 0x0035) & 0xF0FF)
763 bcm43xx_phy_write(bcm, 0x0038, 0x0667);
767 bcm43xx_radio_write16(bcm, 0x007A,
768 bcm43xx_radio_read16(bcm, 0x007A)
770 bcm43xx_radio_write16(bcm, 0x0051,
771 bcm43xx_radio_read16(bcm, 0x0051)
774 bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_RADIO, 0x0000);
776 bcm43xx_phy_write(bcm, 0x0802, bcm43xx_phy_read(bcm, 0x0802) | 0x0100);
777 bcm43xx_phy_write(bcm, 0x042B, bcm43xx_phy_read(bcm, 0x042B) | 0x2000);
779 bcm43xx_phy_write(bcm, 0x001C, 0x186A);
781 bcm43xx_phy_write(bcm, 0x0013, (bcm43xx_phy_read(bcm, 0x0013) & 0x00FF) | 0x1900);
782 bcm43xx_phy_write(bcm, 0x0035, (bcm43xx_phy_read(bcm, 0x0035) & 0xFFC0) | 0x0064);
783 bcm43xx_phy_write(bcm, 0x005D, (bcm43xx_phy_read(bcm, 0x005D) & 0xFF80) | 0x000A);
786 if (bcm->bad_frames_preempt) {
787 bcm43xx_phy_write(bcm, BCM43xx_PHY_RADIO_BITFIELD,
788 bcm43xx_phy_read(bcm, BCM43xx_PHY_RADIO_BITFIELD) | (1 << 11));
792 bcm43xx_phy_write(bcm, 0x0026, 0xCE00);
793 bcm43xx_phy_write(bcm, 0x0021, 0x3763);
794 bcm43xx_phy_write(bcm, 0x0022, 0x1BC3);
795 bcm43xx_phy_write(bcm, 0x0023, 0x06F9);
796 bcm43xx_phy_write(bcm, 0x0024, 0x037E);
798 bcm43xx_phy_write(bcm, 0x0026, 0xCC00);
799 bcm43xx_phy_write(bcm, 0x0030, 0x00C6);
800 bcm43xx_write16(bcm, 0x03EC, 0x3F22);
803 bcm43xx_phy_write(bcm, 0x0020, 0x3E1C);
805 bcm43xx_phy_write(bcm, 0x0020, 0x301C);
808 bcm43xx_write16(bcm, 0x03E4, 0x3000);
812 bcm43xx_radio_selectchannel(bcm, 7, 0);
815 bcm43xx_radio_write16(bcm, 0x0075, 0x0080);
816 bcm43xx_radio_write16(bcm, 0x0079, 0x0081);
819 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
820 bcm43xx_radio_write16(bcm, 0x0050, 0x0023);
823 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
824 bcm43xx_radio_write16(bcm, 0x005A, 0x0070);
827 bcm43xx_radio_write16(bcm, 0x005B, 0x007B);
828 bcm43xx_radio_write16(bcm, 0x005C, 0x00B0);
830 bcm43xx_radio_write16(bcm, 0x007A, bcm43xx_radio_read16(bcm, 0x007A) | 0x0007);
832 bcm43xx_radio_selectchannel(bcm, old_channel, 0);
834 bcm43xx_phy_write(bcm, 0x0014, 0x0080);
835 bcm43xx_phy_write(bcm, 0x0032, 0x00CA);
836 bcm43xx_phy_write(bcm, 0x002A, 0x88A3);
838 bcm43xx_radio_set_txpower_bg(bcm, 0xFFFF, 0xFFFF, 0xFFFF);
841 bcm43xx_radio_write16(bcm, 0x005D, 0x000D);
843 bcm43xx_write16(bcm, 0x03E4, (bcm43xx_read16(bcm, 0x03E4) & 0xFFC0) | 0x0004);
846 static void bcm43xx_phy_initb6(struct bcm43xx_private *bcm)
848 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
849 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
853 bcm43xx_phy_write(bcm, 0x003E, 0x817A);
854 bcm43xx_radio_write16(bcm, 0x007A,
855 (bcm43xx_radio_read16(bcm, 0x007A) | 0x0058));
858 bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
859 bcm43xx_radio_write16(bcm, 0x0052, 0x0070);
860 bcm43xx_radio_write16(bcm, 0x0053, 0x00B3);
861 bcm43xx_radio_write16(bcm, 0x0054, 0x009B);
862 bcm43xx_radio_write16(bcm, 0x005A, 0x0088);
863 bcm43xx_radio_write16(bcm, 0x005B, 0x0088);
864 bcm43xx_radio_write16(bcm, 0x005D, 0x0088);
865 bcm43xx_radio_write16(bcm, 0x005E, 0x0088);
866 bcm43xx_radio_write16(bcm, 0x007D, 0x0088);
867 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
869 (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
874 bcm43xx_radio_write16(bcm, 0x0051, 0x0000);
875 bcm43xx_radio_write16(bcm, 0x0052, 0x0040);
876 bcm43xx_radio_write16(bcm, 0x0053, 0x00B7);
877 bcm43xx_radio_write16(bcm, 0x0054, 0x0098);
878 bcm43xx_radio_write16(bcm, 0x005A, 0x0088);
879 bcm43xx_radio_write16(bcm, 0x005B, 0x006B);
880 bcm43xx_radio_write16(bcm, 0x005C, 0x000F);
881 if (bcm->sprom.boardflags & 0x8000) {
882 bcm43xx_radio_write16(bcm, 0x005D, 0x00FA);
883 bcm43xx_radio_write16(bcm, 0x005E, 0x00D8);
885 bcm43xx_radio_write16(bcm, 0x005D, 0x00F5);
886 bcm43xx_radio_write16(bcm, 0x005E, 0x00B8);
888 bcm43xx_radio_write16(bcm, 0x0073, 0x0003);
889 bcm43xx_radio_write16(bcm, 0x007D, 0x00A8);
890 bcm43xx_radio_write16(bcm, 0x007C, 0x0001);
891 bcm43xx_radio_write16(bcm, 0x007E, 0x0008);
895 bcm43xx_phy_write(bcm, offset, val);
900 bcm43xx_phy_write(bcm, offset, val);
905 bcm43xx_phy_write(bcm, offset, (val & 0x3F3F));
909 bcm43xx_radio_write16(bcm, 0x007A,
910 bcm43xx_radio_read16(bcm, 0x007A) | 0x0020);
911 bcm43xx_radio_write16(bcm, 0x0051,
912 bcm43xx_radio_read16(bcm, 0x0051) | 0x0004);
913 bcm43xx_phy_write(bcm, 0x0802,
914 bcm43xx_phy_read(bcm, 0x0802) | 0x0100);
915 bcm43xx_phy_write(bcm, 0x042B,
916 bcm43xx_phy_read(bcm, 0x042B) | 0x2000);
917 bcm43xx_phy_write(bcm, 0x5B, 0x0000);
918 bcm43xx_phy_write(bcm, 0x5C, 0x0000);
923 bcm43xx_radio_selectchannel(bcm, 1, 0);
925 bcm43xx_radio_selectchannel(bcm, 13, 0);
927 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
928 bcm43xx_radio_write16(bcm, 0x0050, 0x0023);
931 bcm43xx_radio_write16(bcm, 0x007C, (bcm43xx_radio_read16(bcm, 0x007C)
933 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
936 bcm43xx_radio_write16(bcm, 0x007C, 0x0020);
937 bcm43xx_radio_write16(bcm, 0x005A, 0x0070);
938 bcm43xx_radio_write16(bcm, 0x005B, 0x007B);
939 bcm43xx_radio_write16(bcm, 0x005C, 0x00B0);
941 bcm43xx_radio_write16(bcm, 0x007A,
942 (bcm43xx_radio_read16(bcm, 0x007A) & 0x00F8) | 0x0007);
944 bcm43xx_radio_selectchannel(bcm, old_channel, 0);
946 bcm43xx_phy_write(bcm, 0x0014, 0x0200);
948 bcm43xx_phy_write(bcm, 0x002A, 0x88C2);
950 bcm43xx_phy_write(bcm, 0x002A, 0x8AC0);
951 bcm43xx_phy_write(bcm, 0x0038, 0x0668);
952 bcm43xx_radio_set_txpower_bg(bcm, 0xFFFF, 0xFFFF, 0xFFFF);
954 bcm43xx_phy_write(bcm, 0x005D, (bcm43xx_phy_read(bcm, 0x005D)
957 bcm43xx_radio_write16(bcm, 0x005D, 0x000D);
960 bcm43xx_write16(bcm, 0x03E4, 0x0009);
961 bcm43xx_phy_write(bcm, 0x61, bcm43xx_phy_read(bcm, 0x61) & 0xFFF);
963 bcm43xx_phy_write(bcm, 0x0002, (bcm43xx_phy_read(bcm, 0x0002) & 0xFFC0) | 0x0004);
966 bcm43xx_write16(bcm, 0x03E6, 0x0);
968 bcm43xx_write16(bcm, 0x03E6, 0x8140);
969 bcm43xx_phy_write(bcm, 0x0016, 0x0410);
970 bcm43xx_phy_write(bcm, 0x0017, 0x0820);
971 bcm43xx_phy_write(bcm, 0x0062, 0x0007);
972 bcm43xx_radio_init2050(bcm);
973 bcm43xx_phy_lo_g_measure(bcm);
974 if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
975 bcm43xx_calc_nrssi_slope(bcm);
976 bcm43xx_calc_nrssi_threshold(bcm);
978 bcm43xx_phy_init_pctl(bcm);
982 static void bcm43xx_calc_loopback_gain(struct bcm43xx_private *bcm)
984 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
985 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
993 backup_phy[0] = bcm43xx_phy_read(bcm, 0x0429);
994 backup_phy[1] = bcm43xx_phy_read(bcm, 0x0001);
995 backup_phy[2] = bcm43xx_phy_read(bcm, 0x0811);
996 backup_phy[3] = bcm43xx_phy_read(bcm, 0x0812);
998 backup_phy[4] = bcm43xx_phy_read(bcm, 0x0814);
999 backup_phy[5] = bcm43xx_phy_read(bcm, 0x0815);
1001 backup_phy[6] = bcm43xx_phy_read(bcm, 0x005A);
1002 backup_phy[7] = bcm43xx_phy_read(bcm, 0x0059);
1003 backup_phy[8] = bcm43xx_phy_read(bcm, 0x0058);
1004 backup_phy[9] = bcm43xx_phy_read(bcm, 0x000A);
1005 backup_phy[10] = bcm43xx_phy_read(bcm, 0x0003);
1006 backup_phy[11] = bcm43xx_phy_read(bcm, 0x080F);
1007 backup_phy[12] = bcm43xx_phy_read(bcm, 0x0810);
1008 backup_phy[13] = bcm43xx_phy_read(bcm, 0x002B);
1009 backup_phy[14] = bcm43xx_phy_read(bcm, 0x0015);
1010 bcm43xx_phy_read(bcm, 0x002D); /* dummy read */
1012 backup_radio[0] = bcm43xx_radio_read16(bcm, 0x0052);
1013 backup_radio[1] = bcm43xx_radio_read16(bcm, 0x0043);
1014 backup_radio[2] = bcm43xx_radio_read16(bcm, 0x007A);
1016 bcm43xx_phy_write(bcm, 0x0429,
1017 bcm43xx_phy_read(bcm, 0x0429) & 0x3FFF);
1018 bcm43xx_phy_write(bcm, 0x0001,
1019 bcm43xx_phy_read(bcm, 0x0001) & 0x8000);
1020 bcm43xx_phy_write(bcm, 0x0811,
1021 bcm43xx_phy_read(bcm, 0x0811) | 0x0002);
1022 bcm43xx_phy_write(bcm, 0x0812,
1023 bcm43xx_phy_read(bcm, 0x0812) & 0xFFFD);
1024 bcm43xx_phy_write(bcm, 0x0811,
1025 bcm43xx_phy_read(bcm, 0x0811) | 0x0001);
1026 bcm43xx_phy_write(bcm, 0x0812,
1027 bcm43xx_phy_read(bcm, 0x0812) & 0xFFFE);
1029 bcm43xx_phy_write(bcm, 0x0814,
1030 bcm43xx_phy_read(bcm, 0x0814) | 0x0001);
1031 bcm43xx_phy_write(bcm, 0x0815,
1032 bcm43xx_phy_read(bcm, 0x0815) & 0xFFFE);
1033 bcm43xx_phy_write(bcm, 0x0814,
1034 bcm43xx_phy_read(bcm, 0x0814) | 0x0002);
1035 bcm43xx_phy_write(bcm, 0x0815,
1036 bcm43xx_phy_read(bcm, 0x0815) & 0xFFFD);
1038 bcm43xx_phy_write(bcm, 0x0811,
1039 bcm43xx_phy_read(bcm, 0x0811) | 0x000C);
1040 bcm43xx_phy_write(bcm, 0x0812,
1041 bcm43xx_phy_read(bcm, 0x0812) | 0x000C);
1043 bcm43xx_phy_write(bcm, 0x0811,
1044 (bcm43xx_phy_read(bcm, 0x0811)
1046 bcm43xx_phy_write(bcm, 0x0812,
1047 (bcm43xx_phy_read(bcm, 0x0812)
1050 bcm43xx_phy_write(bcm, 0x005A, 0x0780);
1051 bcm43xx_phy_write(bcm, 0x0059, 0xC810);
1052 bcm43xx_phy_write(bcm, 0x0058, 0x000D);
1054 bcm43xx_phy_write(bcm, 0x0003, 0x0122);
1056 bcm43xx_phy_write(bcm, 0x000A,
1057 bcm43xx_phy_read(bcm, 0x000A)
1061 bcm43xx_phy_write(bcm, 0x0814,
1062 bcm43xx_phy_read(bcm, 0x0814) | 0x0004);
1063 bcm43xx_phy_write(bcm, 0x0815,
1064 bcm43xx_phy_read(bcm, 0x0815) & 0xFFFB);
1066 bcm43xx_phy_write(bcm, 0x0003,
1067 (bcm43xx_phy_read(bcm, 0x0003)
1070 bcm43xx_radio_write16(bcm, 0x0052, 0x0000);
1071 bcm43xx_radio_write16(bcm, 0x0043,
1072 (bcm43xx_radio_read16(bcm, 0x0043)
1076 bcm43xx_radio_write16(bcm, 0x0043, 0x000F);
1081 bcm43xx_phy_set_baseband_attenuation(bcm, 11);
1084 bcm43xx_phy_write(bcm, 0x080F, 0xC020);
1086 bcm43xx_phy_write(bcm, 0x080F, 0x8020);
1087 bcm43xx_phy_write(bcm, 0x0810, 0x0000);
1089 bcm43xx_phy_write(bcm, 0x002B,
1090 (bcm43xx_phy_read(bcm, 0x002B)
1092 bcm43xx_phy_write(bcm, 0x002B,
1093 (bcm43xx_phy_read(bcm, 0x002B)
1095 bcm43xx_phy_write(bcm, 0x0811,
1096 bcm43xx_phy_read(bcm, 0x0811) | 0x0100);
1097 bcm43xx_phy_write(bcm, 0x0812,
1098 bcm43xx_phy_read(bcm, 0x0812) & 0xCFFF);
1099 if (bcm->sprom.boardflags & BCM43xx_BFL_EXTLNA) {
1101 bcm43xx_phy_write(bcm, 0x0811,
1102 bcm43xx_phy_read(bcm, 0x0811)
1104 bcm43xx_phy_write(bcm, 0x0812,
1105 bcm43xx_phy_read(bcm, 0x0812)
1109 bcm43xx_radio_write16(bcm, 0x007A,
1110 bcm43xx_radio_read16(bcm, 0x007A)
1114 bcm43xx_radio_write16(bcm, 0x0043, loop1_cnt);
1115 bcm43xx_phy_write(bcm, 0x0812,
1116 (bcm43xx_phy_read(bcm, 0x0812)
1118 bcm43xx_phy_write(bcm, 0x0015,
1119 (bcm43xx_phy_read(bcm, 0x0015)
1121 bcm43xx_phy_write(bcm, 0x0015,
1122 (bcm43xx_phy_read(bcm, 0x0015)
1125 if (bcm43xx_phy_read(bcm, 0x002D) >= 0x0DFC)
1133 bcm43xx_phy_write(bcm, 0x0812,
1134 bcm43xx_phy_read(bcm, 0x0812)
1137 bcm43xx_phy_write(bcm, 0x0812,
1138 (bcm43xx_phy_read(bcm, 0x0812)
1140 bcm43xx_phy_write(bcm, 0x0015,
1141 (bcm43xx_phy_read(bcm, 0x0015)
1143 bcm43xx_phy_write(bcm, 0x0015,
1144 (bcm43xx_phy_read(bcm, 0x0015)
1147 if (bcm43xx_phy_read(bcm, 0x002D) >= 0x0DFC)
1153 bcm43xx_phy_write(bcm, 0x0814, backup_phy[4]);
1154 bcm43xx_phy_write(bcm, 0x0815, backup_phy[5]);
1156 bcm43xx_phy_write(bcm, 0x005A, backup_phy[6]);
1157 bcm43xx_phy_write(bcm, 0x0059, backup_phy[7]);
1158 bcm43xx_phy_write(bcm, 0x0058, backup_phy[8]);
1159 bcm43xx_phy_write(bcm, 0x000A, backup_phy[9]);
1160 bcm43xx_phy_write(bcm, 0x0003, backup_phy[10]);
1161 bcm43xx_phy_write(bcm, 0x080F, backup_phy[11]);
1162 bcm43xx_phy_write(bcm, 0x0810, backup_phy[12]);
1163 bcm43xx_phy_write(bcm, 0x002B, backup_phy[13]);
1164 bcm43xx_phy_write(bcm, 0x0015, backup_phy[14]);
1166 bcm43xx_phy_set_baseband_attenuation(bcm, backup_bband);
1168 bcm43xx_radio_write16(bcm, 0x0052, backup_radio[0]);
1169 bcm43xx_radio_write16(bcm, 0x0043, backup_radio[1]);
1170 bcm43xx_radio_write16(bcm, 0x007A, backup_radio[2]);
1172 bcm43xx_phy_write(bcm, 0x0811, backup_phy[2] | 0x0003);
1174 bcm43xx_phy_write(bcm, 0x0811, backup_phy[2]);
1175 bcm43xx_phy_write(bcm, 0x0812, backup_phy[3]);
1176 bcm43xx_phy_write(bcm, 0x0429, backup_phy[0]);
1177 bcm43xx_phy_write(bcm, 0x0001, backup_phy[1]);
1183 static void bcm43xx_phy_initg(struct bcm43xx_private *bcm)
1185 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1186 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1190 bcm43xx_phy_initb5(bcm);
1192 bcm43xx_phy_initb6(bcm);
1194 bcm43xx_phy_inita(bcm);
1197 bcm43xx_phy_write(bcm, 0x0814, 0x0000);
1198 bcm43xx_phy_write(bcm, 0x0815, 0x0000);
1201 bcm43xx_phy_write(bcm, 0x0811, 0x0000);
1202 bcm43xx_phy_write(bcm, 0x0015, 0x00C0);
1205 bcm43xx_phy_write(bcm, 0x0811, 0x0400);
1206 bcm43xx_phy_write(bcm, 0x0015, 0x00C0);
1209 tmp = bcm43xx_phy_read(bcm, 0x0400) & 0xFF;
1211 bcm43xx_phy_write(bcm, 0x04C2, 0x1816);
1212 bcm43xx_phy_write(bcm, 0x04C3, 0x8006);
1214 bcm43xx_phy_write(bcm, 0x04CC,
1215 (bcm43xx_phy_read(bcm, 0x04CC)
1219 bcm43xx_phy_write(bcm, 0x047E, 0x0078);
1222 bcm43xx_phy_write(bcm, 0x0801, bcm43xx_phy_read(bcm, 0x0801) | 0x0080);
1223 bcm43xx_phy_write(bcm, 0x043E, bcm43xx_phy_read(bcm, 0x043E) | 0x0004);
1226 bcm43xx_calc_loopback_gain(bcm);
1229 radio->initval = bcm43xx_radio_init2050(bcm);
1231 bcm43xx_radio_write16(bcm, 0x0078, radio->initval);
1234 bcm43xx_phy_lo_g_measure(bcm);
1237 bcm43xx_radio_write16(bcm, 0x0052,
1240 bcm43xx_radio_write16(bcm, 0x0052,
1241 (bcm43xx_radio_read16(bcm, 0x0052)
1245 bcm43xx_phy_write(bcm, 0x0036,
1246 (bcm43xx_phy_read(bcm, 0x0036)
1249 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
1250 bcm43xx_phy_write(bcm, 0x002E, 0x8075);
1252 bcm43xx_phy_write(bcm, 0x002E, 0x807F);
1254 bcm43xx_phy_write(bcm, 0x002F, 0x0101);
1256 bcm43xx_phy_write(bcm, 0x002F, 0x0202);
1259 bcm43xx_phy_lo_adjust(bcm, 0);
1260 bcm43xx_phy_write(bcm, 0x080F, 0x8078);
1263 if (!(bcm->sprom.boardflags & BCM43xx_BFL_RSSI)) {
1270 bcm43xx_nrssi_hw_update(bcm, 0xFFFF);
1271 bcm43xx_calc_nrssi_threshold(bcm);
1275 bcm43xx_calc_nrssi_slope(bcm);
1278 bcm43xx_calc_nrssi_threshold(bcm);
1282 bcm43xx_phy_write(bcm, 0x0805, 0x3230);
1283 bcm43xx_phy_init_pctl(bcm);
1284 if (bcm->chip_id == 0x4306 && bcm->chip_package == 2) {
1285 bcm43xx_phy_write(bcm, 0x0429,
1286 bcm43xx_phy_read(bcm, 0x0429) & 0xBFFF);
1287 bcm43xx_phy_write(bcm, 0x04C3,
1288 bcm43xx_phy_read(bcm, 0x04C3) & 0x7FFF);
1292 static u16 bcm43xx_phy_lo_b_r15_loop(struct bcm43xx_private *bcm)
1300 bcm43xx_phy_write(bcm, 0x0015, 0xAFA0);
1302 bcm43xx_phy_write(bcm, 0x0015, 0xEFA0);
1304 bcm43xx_phy_write(bcm, 0x0015, 0xFFA0);
1306 ret += bcm43xx_phy_read(bcm, 0x002C);
1314 void bcm43xx_phy_lo_b_measure(struct bcm43xx_private *bcm)
1316 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1317 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1323 regstack[0] = bcm43xx_phy_read(bcm, 0x0015);
1324 regstack[1] = bcm43xx_radio_read16(bcm, 0x0052) & 0xFFF0;
1327 regstack[2] = bcm43xx_phy_read(bcm, 0x000A);
1328 regstack[3] = bcm43xx_phy_read(bcm, 0x002A);
1329 regstack[4] = bcm43xx_phy_read(bcm, 0x0035);
1330 regstack[5] = bcm43xx_phy_read(bcm, 0x0003);
1331 regstack[6] = bcm43xx_phy_read(bcm, 0x0001);
1332 regstack[7] = bcm43xx_phy_read(bcm, 0x0030);
1334 regstack[8] = bcm43xx_radio_read16(bcm, 0x0043);
1335 regstack[9] = bcm43xx_radio_read16(bcm, 0x007A);
1336 regstack[10] = bcm43xx_read16(bcm, 0x03EC);
1337 regstack[11] = bcm43xx_radio_read16(bcm, 0x0052) & 0x00F0;
1339 bcm43xx_phy_write(bcm, 0x0030, 0x00FF);
1340 bcm43xx_write16(bcm, 0x03EC, 0x3F3F);
1341 bcm43xx_phy_write(bcm, 0x0035, regstack[4] & 0xFF7F);
1342 bcm43xx_radio_write16(bcm, 0x007A, regstack[9] & 0xFFF0);
1344 bcm43xx_phy_write(bcm, 0x0015, 0xB000);
1345 bcm43xx_phy_write(bcm, 0x002B, 0x0004);
1348 bcm43xx_phy_write(bcm, 0x002B, 0x0203);
1349 bcm43xx_phy_write(bcm, 0x002A, 0x08A3);
1355 bcm43xx_radio_write16(bcm, 0x0052, regstack[1] | i);
1356 bcm43xx_phy_lo_b_r15_loop(bcm);
1359 bcm43xx_radio_write16(bcm, 0x0052, regstack[1] | i);
1360 mls = bcm43xx_phy_lo_b_r15_loop(bcm) / 10;
1366 bcm43xx_radio_write16(bcm, 0x0052, regstack[1] | phy->minlowsigpos[0]);
1376 bcm43xx_phy_write(bcm, 0x002F, fval);
1377 mls = bcm43xx_phy_lo_b_r15_loop(bcm) / 10;
1386 bcm43xx_phy_write(bcm, 0x002F, phy->minlowsigpos[1]);
1388 bcm43xx_phy_write(bcm, 0x000A, regstack[2]);
1389 bcm43xx_phy_write(bcm, 0x002A, regstack[3]);
1390 bcm43xx_phy_write(bcm, 0x0035, regstack[4]);
1391 bcm43xx_phy_write(bcm, 0x0003, regstack[5]);
1392 bcm43xx_phy_write(bcm, 0x0001, regstack[6]);
1393 bcm43xx_phy_write(bcm, 0x0030, regstack[7]);
1395 bcm43xx_radio_write16(bcm, 0x0043, regstack[8]);
1396 bcm43xx_radio_write16(bcm, 0x007A, regstack[9]);
1398 bcm43xx_radio_write16(bcm, 0x0052,
1399 (bcm43xx_radio_read16(bcm, 0x0052) & 0x000F)
1402 bcm43xx_write16(bcm, 0x03EC, regstack[10]);
1404 bcm43xx_phy_write(bcm, 0x0015, regstack[0]);
1408 u16 bcm43xx_phy_lo_g_deviation_subval(struct bcm43xx_private *bcm, u16 control)
1410 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1416 bcm43xx_phy_write(bcm, 0x15, 0xE300);
1418 bcm43xx_phy_write(bcm, 0x0812, control | 0x00B0);
1420 bcm43xx_phy_write(bcm, 0x0812, control | 0x00B2);
1422 bcm43xx_phy_write(bcm, 0x0812, control | 0x00B3);
1424 bcm43xx_phy_write(bcm, 0x0015, 0xF300);
1427 bcm43xx_phy_write(bcm, 0x0015, control | 0xEFA0);
1429 bcm43xx_phy_write(bcm, 0x0015, control | 0xEFE0);
1431 bcm43xx_phy_write(bcm, 0x0015, control | 0xFFE0);
1434 ret = bcm43xx_phy_read(bcm, 0x002D);
1441 static u32 bcm43xx_phy_lo_g_singledeviation(struct bcm43xx_private *bcm, u16 control)
1447 ret += bcm43xx_phy_lo_g_deviation_subval(bcm, control);
1454 void bcm43xx_lo_write(struct bcm43xx_private *bcm,
1470 (unsigned long)(pair - bcm43xx_current_phy(bcm)->_lo_pairs));
1475 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_LO_CONTROL, value);
1479 struct bcm43xx_lopair * bcm43xx_find_lopair(struct bcm43xx_private *bcm,
1485 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1500 struct bcm43xx_lopair * bcm43xx_current_lopair(struct bcm43xx_private *bcm)
1502 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1504 return bcm43xx_find_lopair(bcm,
1511 void bcm43xx_phy_lo_adjust(struct bcm43xx_private *bcm, int fixed)
1517 pair = bcm43xx_find_lopair(bcm, 2, 3, 0);
1519 pair = bcm43xx_current_lopair(bcm);
1520 bcm43xx_lo_write(bcm, pair);
1523 static void bcm43xx_phy_lo_g_measure_txctl2(struct bcm43xx_private *bcm)
1525 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1529 bcm43xx_radio_write16(bcm, 0x0052, 0x0000);
1531 smallest = bcm43xx_phy_lo_g_singledeviation(bcm, 0);
1533 bcm43xx_radio_write16(bcm, 0x0052, i);
1535 tmp = bcm43xx_phy_lo_g_singledeviation(bcm, 0);
1545 void bcm43xx_phy_lo_g_state(struct bcm43xx_private *bcm,
1575 bcm43xx_lo_write(bcm, &lowest_transition);
1576 lowest_deviation = bcm43xx_phy_lo_g_singledeviation(bcm, r27);
1603 bcm43xx_lo_write(bcm, &transition);
1604 tmp = bcm43xx_phy_lo_g_singledeviation(bcm, r27);
1628 void bcm43xx_phy_set_baseband_attenuation(struct bcm43xx_private *bcm,
1631 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1635 value = (bcm43xx_read16(bcm, 0x03E6) & 0xFFF0);
1637 bcm43xx_write16(bcm, 0x03E6, value);
1642 value = bcm43xx_phy_read(bcm, 0x0060) & ~0x003C;
1645 value = bcm43xx_phy_read(bcm, 0x0060) & ~0x0078;
1648 bcm43xx_phy_write(bcm, 0x0060, value);
1651 /* http://bcm-specs.sipsolutions.net/LocalOscillator/Measure */
1652 void bcm43xx_phy_lo_g_measure(struct bcm43xx_private *bcm)
1655 const int is_initializing = (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZING);
1656 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1657 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1670 regstack[0] = bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS);
1671 regstack[1] = bcm43xx_phy_read(bcm, 0x0802);
1672 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS, regstack[0] & 0x7FFF);
1673 bcm43xx_phy_write(bcm, 0x0802, regstack[1] & 0xFFFC);
1675 regstack[3] = bcm43xx_read16(bcm, 0x03E2);
1676 bcm43xx_write16(bcm, 0x03E2, regstack[3] | 0x8000);
1677 regstack[4] = bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT);
1678 regstack[5] = bcm43xx_phy_read(bcm, 0x15);
1679 regstack[6] = bcm43xx_phy_read(bcm, 0x2A);
1680 regstack[7] = bcm43xx_phy_read(bcm, 0x35);
1681 regstack[8] = bcm43xx_phy_read(bcm, 0x60);
1682 regstack[9] = bcm43xx_radio_read16(bcm, 0x43);
1683 regstack[10] = bcm43xx_radio_read16(bcm, 0x7A);
1684 regstack[11] = bcm43xx_radio_read16(bcm, 0x52);
1686 regstack[12] = bcm43xx_phy_read(bcm, 0x0811);
1687 regstack[13] = bcm43xx_phy_read(bcm, 0x0812);
1688 regstack[14] = bcm43xx_phy_read(bcm, 0x0814);
1689 regstack[15] = bcm43xx_phy_read(bcm, 0x0815);
1691 bcm43xx_radio_selectchannel(bcm, 6, 0);
1693 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS, regstack[0] & 0x7FFF);
1694 bcm43xx_phy_write(bcm, 0x0802, regstack[1] & 0xFFFC);
1695 bcm43xx_dummy_transmission(bcm);
1697 bcm43xx_radio_write16(bcm, 0x0043, 0x0006);
1699 bcm43xx_phy_set_baseband_attenuation(bcm, 2);
1701 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT, 0x0000);
1702 bcm43xx_phy_write(bcm, 0x002E, 0x007F);
1703 bcm43xx_phy_write(bcm, 0x080F, 0x0078);
1704 bcm43xx_phy_write(bcm, 0x0035, regstack[7] & ~(1 << 7));
1705 bcm43xx_radio_write16(bcm, 0x007A, regstack[10] & 0xFFF0);
1706 bcm43xx_phy_write(bcm, 0x002B, 0x0203);
1707 bcm43xx_phy_write(bcm, 0x002A, 0x08A3);
1709 bcm43xx_phy_write(bcm, 0x0814, regstack[14] | 0x0003);
1710 bcm43xx_phy_write(bcm, 0x0815, regstack[15] & 0xFFFC);
1711 bcm43xx_phy_write(bcm, 0x0811, 0x01B3);
1712 bcm43xx_phy_write(bcm, 0x0812, 0x00B2);
1715 bcm43xx_phy_lo_g_measure_txctl2(bcm);
1716 bcm43xx_phy_write(bcm, 0x080F, 0x8078);
1758 bcm43xx_radio_write16(bcm, 0x43, i);
1759 bcm43xx_radio_write16(bcm, 0x52, radio->txctl2);
1763 bcm43xx_phy_set_baseband_attenuation(bcm, j * 2);
1768 bcm43xx_radio_write16(bcm, 0x007A, tmp);
1771 bcm43xx_phy_lo_g_state(bcm, &control, tmp_control, r27);
1800 bcm43xx_radio_write16(bcm, 0x43, i - 9);
1801 bcm43xx_radio_write16(bcm, 0x52,
1807 bcm43xx_phy_set_baseband_attenuation(bcm, j * 2);
1812 bcm43xx_radio_write16(bcm, 0x7A, tmp);
1815 bcm43xx_phy_lo_g_state(bcm, &control, tmp_control, r27);
1821 bcm43xx_phy_write(bcm, 0x0015, 0xE300);
1822 bcm43xx_phy_write(bcm, 0x0812, (r27 << 8) | 0xA0);
1824 bcm43xx_phy_write(bcm, 0x0812, (r27 << 8) | 0xA2);
1826 bcm43xx_phy_write(bcm, 0x0812, (r27 << 8) | 0xA3);
1829 bcm43xx_phy_write(bcm, 0x0015, r27 | 0xEFA0);
1830 bcm43xx_phy_lo_adjust(bcm, is_initializing);
1831 bcm43xx_phy_write(bcm, 0x002E, 0x807F);
1833 bcm43xx_phy_write(bcm, 0x002F, 0x0202);
1835 bcm43xx_phy_write(bcm, 0x002F, 0x0101);
1836 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT, regstack[4]);
1837 bcm43xx_phy_write(bcm, 0x0015, regstack[5]);
1838 bcm43xx_phy_write(bcm, 0x002A, regstack[6]);
1839 bcm43xx_phy_write(bcm, 0x0035, regstack[7]);
1840 bcm43xx_phy_write(bcm, 0x0060, regstack[8]);
1841 bcm43xx_radio_write16(bcm, 0x0043, regstack[9]);
1842 bcm43xx_radio_write16(bcm, 0x007A, regstack[10]);
1844 regstack[11] |= (bcm43xx_radio_read16(bcm, 0x52) & 0x000F);
1845 bcm43xx_radio_write16(bcm, 0x52, regstack[11]);
1846 bcm43xx_write16(bcm, 0x03E2, regstack[3]);
1848 bcm43xx_phy_write(bcm, 0x0811, regstack[12]);
1849 bcm43xx_phy_write(bcm, 0x0812, regstack[13]);
1850 bcm43xx_phy_write(bcm, 0x0814, regstack[14]);
1851 bcm43xx_phy_write(bcm, 0x0815, regstack[15]);
1852 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS, regstack[0]);
1853 bcm43xx_phy_write(bcm, 0x0802, regstack[1]);
1855 bcm43xx_radio_selectchannel(bcm, oldchannel, 1);
1874 void bcm43xx_phy_lo_mark_current_used(struct bcm43xx_private *bcm)
1878 pair = bcm43xx_current_lopair(bcm);
1882 void bcm43xx_phy_lo_mark_all_unused(struct bcm43xx_private *bcm)
1884 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1894 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
1897 static s8 bcm43xx_phy_estimate_power_out(struct bcm43xx_private *bcm, s8 tssi)
1899 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1926 /* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
1927 void bcm43xx_phy_xmitpower(struct bcm43xx_private *bcm)
1929 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1930 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1934 if ((bcm->board_type == 0x0416) &&
1935 (bcm->board_vendor == PCI_VENDOR_ID_BROADCOM))
1957 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x0058);
1960 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x005A);
1966 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x0070);
1969 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x0072);
1980 bcm43xx_radio_clear_tssi(bcm);
1984 if (tmp && (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x005E) & 0x8))
1987 estimated_pwr = bcm43xx_phy_estimate_power_out(bcm, average);
1989 max_pwr = bcm->sprom.maxpower_bgphy;
1991 if ((bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) &&
1996 max_pwr = min(REG - bcm->sprom.antennagain_bgphy - 0x6, max_pwr)
2006 bcm43xx_phy_lo_mark_current_used(bcm);
2045 } else if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
2064 bcm43xx_phy_lock(bcm, phylock_flags);
2065 bcm43xx_radio_lock(bcm);
2066 bcm43xx_radio_set_txpower_bg(bcm, baseband_attenuation,
2068 bcm43xx_phy_lo_mark_current_used(bcm);
2069 bcm43xx_radio_unlock(bcm);
2070 bcm43xx_phy_unlock(bcm, phylock_flags);
2108 /* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
2109 int bcm43xx_phy_init_tssi2dbm_table(struct bcm43xx_private *bcm)
2111 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2112 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2118 pab0 = (s16)(bcm->sprom.pa1b0);
2119 pab1 = (s16)(bcm->sprom.pa1b1);
2120 pab2 = (s16)(bcm->sprom.pa1b2);
2122 pab0 = (s16)(bcm->sprom.pa0b0);
2123 pab1 = (s16)(bcm->sprom.pa0b1);
2124 pab2 = (s16)(bcm->sprom.pa0b2);
2127 if ((bcm->chip_id == 0x4301) && (radio->version != 0x2050)) {
2137 if ((s8)bcm->sprom.idle_tssi_tgt_aphy != 0 &&
2138 (s8)bcm->sprom.idle_tssi_tgt_aphy != -1)
2139 phy->idle_tssi = (s8)(bcm->sprom.idle_tssi_tgt_aphy);
2143 if ((s8)bcm->sprom.idle_tssi_tgt_bgphy != 0 &&
2144 (s8)bcm->sprom.idle_tssi_tgt_bgphy != -1)
2145 phy->idle_tssi = (s8)(bcm->sprom.idle_tssi_tgt_bgphy);
2188 int bcm43xx_phy_init(struct bcm43xx_private *bcm)
2190 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2196 bcm43xx_phy_inita(bcm);
2203 bcm43xx_phy_initb2(bcm);
2207 bcm43xx_phy_initb4(bcm);
2211 bcm43xx_phy_initb5(bcm);
2215 bcm43xx_phy_initb6(bcm);
2221 bcm43xx_phy_initg(bcm);
2231 void bcm43xx_phy_set_antenna_diversity(struct bcm43xx_private *bcm)
2233 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2245 ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2247 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2263 bcm43xx_phy_write(bcm, offset + 1,
2264 (bcm43xx_phy_read(bcm, offset + 1)
2272 bcm43xx_phy_write(bcm, offset + 0x2B,
2273 (bcm43xx_phy_read(bcm, offset + 0x2B)
2279 bcm43xx_phy_write(bcm, 0x048C,
2280 bcm43xx_phy_read(bcm, 0x048C)
2283 bcm43xx_phy_write(bcm, 0x048C,
2284 bcm43xx_phy_read(bcm, 0x048C)
2287 bcm43xx_phy_write(bcm, 0x0461,
2288 bcm43xx_phy_read(bcm, 0x0461)
2290 bcm43xx_phy_write(bcm, 0x04AD,
2291 (bcm43xx_phy_read(bcm, 0x04AD)
2294 bcm43xx_phy_write(bcm, 0x0427, 0x0008);
2296 bcm43xx_phy_write(bcm, 0x0427,
2297 (bcm43xx_phy_read(bcm, 0x0427)
2301 bcm43xx_phy_write(bcm, 0x049B, 0x00DC);
2304 bcm43xx_phy_write(bcm, 0x002B,
2305 (bcm43xx_phy_read(bcm, 0x002B)
2308 bcm43xx_phy_write(bcm, 0x0061,
2309 bcm43xx_phy_read(bcm, 0x0061)
2312 bcm43xx_phy_write(bcm, 0x0093, 0x001D);
2313 bcm43xx_phy_write(bcm, 0x0027, 0x0008);
2315 bcm43xx_phy_write(bcm, 0x0093, 0x003A);
2316 bcm43xx_phy_write(bcm, 0x0027,
2317 (bcm43xx_phy_read(bcm, 0x0027)
2324 if (bcm->current_core->rev == 2)
2328 bcm43xx_phy_write(bcm, 0x03E2,
2329 (bcm43xx_phy_read(bcm, 0x03E2)
2337 ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2339 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,