Lines Matching refs:bcm
82 netif_stop_queue(ring->bcm->net_dev);
107 netif_wake_queue(ring->bcm->net_dev);
153 dmaaddr = pci_map_single(ring->bcm->pci_dev,
167 pci_unmap_single(ring->bcm->pci_dev,
171 pci_unmap_single(ring->bcm->pci_dev,
184 pci_dma_sync_single_for_cpu(ring->bcm->pci_dev,
195 pci_dma_sync_single_for_cpu(ring->bcm->pci_dev,
215 ring->descbase = pci_alloc_consistent(ring->bcm->pci_dev, BCM43xx_DMA_RINGMEMSIZE,
228 rx_ring_dma = pci_map_single(ring->bcm->pci_dev, rx_ring,
233 rx_ring_dma + BCM43xx_DMA_RINGMEMSIZE > ring->bcm->dma_mask) {
236 pci_unmap_single(ring->bcm->pci_dev,
239 rx_ring_dma = pci_map_single(ring->bcm->pci_dev,
243 rx_ring_dma + BCM43xx_DMA_RINGMEMSIZE > ring->bcm->dma_mask) {
246 pci_unmap_single(ring->bcm->pci_dev,
266 struct device *dev = &(ring->bcm->pci_dev->dev);
273 int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,
281 bcm43xx_write32(bcm, mmio_base + offset, 0);
284 value = bcm43xx_read32(bcm, mmio_base + offset);
309 int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,
318 value = bcm43xx_read32(bcm, mmio_base + offset);
335 bcm43xx_write32(bcm, mmio_base + offset, 0);
338 value = bcm43xx_read32(bcm, mmio_base + offset);
445 dmaaddr + ring->rx_buffersize > ring->bcm->dma_mask) {
448 pci_unmap_single(ring->bcm->pci_dev,
455 dmaaddr = pci_map_single(ring->bcm->pci_dev,
459 dmaaddr + ring->rx_buffersize > ring->bcm->dma_mask) {
467 skb->dev = ring->bcm->net_dev;
592 bcm43xx_dmacontroller_tx_reset(ring->bcm, ring->mmio_base, ring->dma64);
599 bcm43xx_dmacontroller_rx_reset(ring->bcm, ring->mmio_base, ring->dma64);
636 struct bcm43xx_dmaring * bcm43xx_setup_dmaring(struct bcm43xx_private *bcm,
662 ring->bcm = bcm;
728 void bcm43xx_dma_free(struct bcm43xx_private *bcm)
732 if (bcm43xx_using_pio(bcm))
734 dma = bcm43xx_current_dma(bcm);
755 int bcm43xx_dma_init(struct bcm43xx_private *bcm)
757 struct bcm43xx_dma *dma = bcm43xx_current_dma(bcm);
762 bcm->dma_mask = bcm43xx_get_supported_dma_mask(bcm);
763 if (bcm->dma_mask == DMA_64BIT_MASK)
765 err = pci_set_dma_mask(bcm->pci_dev, bcm->dma_mask);
768 err = pci_set_consistent_dma_mask(bcm->pci_dev, bcm->dma_mask);
773 ring = bcm43xx_setup_dmaring(bcm, 0, 1, dma64);
778 ring = bcm43xx_setup_dmaring(bcm, 1, 1, dma64);
783 ring = bcm43xx_setup_dmaring(bcm, 2, 1, dma64);
788 ring = bcm43xx_setup_dmaring(bcm, 3, 1, dma64);
793 ring = bcm43xx_setup_dmaring(bcm, 4, 1, dma64);
798 ring = bcm43xx_setup_dmaring(bcm, 5, 1, dma64);
804 ring = bcm43xx_setup_dmaring(bcm, 0, 0, dma64);
809 if (bcm->current_core->rev < 5) {
810 ring = bcm43xx_setup_dmaring(bcm, 3, 0, dma64);
817 (bcm->dma_mask == DMA_64BIT_MASK) ? 64 :
818 (bcm->dma_mask == DMA_32BIT_MASK) ? 32 : 30);
848 bcm->__using_pio = 1;
897 struct bcm43xx_dmaring * parse_cookie(struct bcm43xx_private *bcm,
900 struct bcm43xx_dma *dma = bcm43xx_current_dma(bcm);
973 bcm43xx_generate_txhdr(ring->bcm,
980 if (dma_mapping_error(dmaaddr) || dmaaddr + skb->len > ring->bcm->dma_mask) {
988 if (dma_mapping_error(dmaaddr) || dmaaddr + skb->len > ring->bcm->dma_mask) {
1011 int bcm43xx_dma_tx(struct bcm43xx_private *bcm,
1019 struct bcm43xx_dmaring *ring = bcm43xx_current_dma(bcm)->tx_ring1;
1044 void bcm43xx_dma_handle_xmitstatus(struct bcm43xx_private *bcm,
1054 ring = parse_cookie(bcm, status->cookie, &slot);
1079 bcm->stats.last_tx = jiffies;
1120 bcm43xx_debugfs_log_txstat(ring->bcm, &stat);
1121 bcm43xx_dma_handle_xmitstatus(ring->bcm, &stat);
1184 err = bcm43xx_rx(ring->bcm, skb, rxhdr);
1236 bcm43xx_power_saving_ctl_bits(ring->bcm, -1, 1);
1260 bcm43xx_power_saving_ctl_bits(ring->bcm, -1, -1);