Lines Matching refs:ti
330 struct tok_info *ti = (struct tok_info *) dev->priv;
331 iounmap(ti->mmio);
332 iounmap(ti->sram_virt);
387 struct tok_info *ti = dev->priv;
431 t_mmio = ti->mmio; /*BMS to get virtual address */
432 irq = ti->irq; /*BMS to display the irq! */
484 ti->mmio = t_mmio;
492 ti->turbo = 1;
496 ti->readlog_pending = 0;
497 init_waitqueue_head(&ti->wait_for_reset);
509 ti->adapter_int_enable = PIOaddr + ADAPTINTREL;
516 ti->global_int_enable = 0;
517 ti->adapter_int_enable = 0;
518 ti->sram_phys=(__u32)(inb(PIOaddr+ADAPTRESETREL) & 0xfe) << 12;
529 while (!readb(ti->mmio + ACA_OFFSET + ACA_RW + RRR_EVEN)){
535 ti->sram_phys =
536 ((__u32)readb(ti->mmio+ACA_OFFSET+ACA_RW+RRR_EVEN)<<12);
537 ti->adapter_int_enable = PIOaddr + ADAPTINTREL;
544 printk(", sram_phys=0x%x", ti->sram_phys);
546 DPRINTK(", ti->mmio=%p", ti->mmio);
556 temp = readb(ti->mmio + AIP + i) & 0x0f;
557 ti->hw_address[j] = temp;
560 ti->hw_address[j]+ (ti->hw_address[j - 1] << 4);
564 ti->adapter_type = readb(ti->mmio + AIPADAPTYPE);
567 ti->data_rate = readb(ti->mmio + AIPDATARATE);
570 ti->token_release = readb(ti->mmio + AIPEARLYTOKEN);
573 if (ti->turbo) {
574 ti->avail_shared_ram=127;
576 ti->avail_shared_ram = get_sram_size(ti);/*in 512 byte units */
580 ti->shared_ram_paging = readb(ti->mmio + AIPSHRAMPAGE);
583 switch (readb(ti->mmio + AIP4MBDHB)) {
584 case 0xe: ti->dhb_size4mb = 4096; break;
585 case 0xd: ti->dhb_size4mb = 4464; break;
586 default: ti->dhb_size4mb = 2048; break;
590 switch (readb(ti->mmio + AIP16MBDHB)) {
591 case 0xe: ti->dhb_size16mb = 4096; break;
592 case 0xd: ti->dhb_size16mb = 8192; break;
593 case 0xc: ti->dhb_size16mb = 16384; break;
594 case 0xb: ti->dhb_size16mb = 17960; break;
595 default: ti->dhb_size16mb = 2048; break;
609 ti->mapped_ram_size= /*sixteen to onehundredtwentyeight 512byte blocks*/
610 1<< ((readb(ti->mmio+ACA_OFFSET+ACA_RW+RRR_ODD) >> 2 & 0x03) + 4);
611 ti->page_mask = 0;
612 if (ti->turbo) ti->page_mask=0xf0;
613 else if (ti->shared_ram_paging == 0xf); /* No paging in adapter */
619 switch (ti->shared_ram_paging) {
623 ti->page_mask = (ti->mapped_ram_size == 32) ? 0xc0 : 0;
627 ti->page_mask = (ti->mapped_ram_size == 64) ? 0x80 : 0;
631 switch (ti->mapped_ram_size) {
633 ti->page_mask = 0xc0;
637 ti->page_mask = 0x80;
644 ti->shared_ram_paging);
654 ti->shared_ram_paging, ti->mapped_ram_size / 2,
655 ti->avail_shared_ram / 2, ti->page_mask);
666 rrr_32=readb(ti->mmio+ACA_OFFSET+ACA_RW+RRR_ODD) >> 2 & 0x03;
669 chk_base = new_base + (ti->mapped_ram_size << 9);
677 ti->sram_base = new_base >> 12;
681 else ti->sram_base = ti->sram_phys >> 12;
705 channel_def[cardpresent - 1], adapter_def(ti->adapter_type));
707 irq, PIOaddr, ti->mapped_ram_size / 2);
711 if (ti->page_mask)
714 ((ti->page_mask^0xff)+1) >>2, ti->avail_shared_ram / 2);
716 DPRINTK("Shared RAM paging disabled. ti->page_mask %x\n",
717 ti->page_mask);
725 if (!ti->page_mask) {
726 ti->avail_shared_ram=
727 min(ti->mapped_ram_size,ti->avail_shared_ram);
730 switch (ti->avail_shared_ram) {
732 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)2048);
733 ti->rbuf_len4 = 1032;
734 ti->rbuf_cnt4=2;
735 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)2048);
736 ti->rbuf_len16 = 1032;
737 ti->rbuf_cnt16=2;
740 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
741 ti->rbuf_len4 = 1032;
742 ti->rbuf_cnt4=4;
743 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)4096);
744 ti->rbuf_len16 = 1032; /*1024 usable */
745 ti->rbuf_cnt16=4;
748 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
749 ti->rbuf_len4 = 1032;
750 ti->rbuf_cnt4=6;
751 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)10240);
752 ti->rbuf_len16 = 1032;
753 ti->rbuf_cnt16=6;
756 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
757 ti->rbuf_len4 = 1032;
758 ti->rbuf_cnt4=6;
759 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)16384);
760 ti->rbuf_len16 = 1032;
761 ti->rbuf_cnt16=16;
764 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
765 ti->rbuf_len4 = 1032;
766 ti->rbuf_cnt4=6;
767 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)17960);
768 ti->rbuf_len16 = 1032;
769 ti->rbuf_cnt16=16;
772 ti->dhb_size4mb = 2048;
773 ti->rbuf_len4 = 1032;
774 ti->rbuf_cnt4=2;
775 ti->dhb_size16mb = 2048;
776 ti->rbuf_len16 = 1032;
777 ti->rbuf_cnt16=2;
781 ti->rbuf_cnt<x> = (ti->avail_shared_ram * BLOCKSZ - ADAPT_PRIVATE -
783 DLC_MAX_STA * STALENGTH - ti->dhb_size<x>mb * NUM_DHB -
784 SRBLENGTH - ASBLENGTH) / ti->rbuf_len<x>;
786 ti->maxmtu16 = (ti->rbuf_len16 - 8) * ti->rbuf_cnt16 - TR_HLEN;
787 ti->maxmtu4 = (ti->rbuf_len4 - 8) * ti->rbuf_cnt4 - TR_HLEN;
790 ti->maxmtu16, ti->maxmtu4);
793 dev->mem_start = ti->sram_base << 12;
794 dev->mem_end = dev->mem_start + (ti->mapped_ram_size << 9) - 1;
826 struct tok_info *ti = (struct tok_info *) dev->priv;
828 SET_PAGE(ti->srb_page);
829 ti->open_failure = NO ;
844 struct tok_info *ti;
849 ti = (struct tok_info *) dev->priv;
851 ti->do_tok_int = FIRST_INT;
853 writeb(~INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_EVEN);
860 if (ti->page_mask)
861 writeb(SRPR_ENABLE_PAGING,ti->mmio+ACA_OFFSET+ACA_RW+SRPR_EVEN);
863 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
864 i = sleep_on_timeout(&ti->wait_for_reset, 4 * HZ);
871 struct tok_info *ti = (struct tok_info *) dev->priv;
875 if (ti->open_failure == YES) {
880 ti->open_status = CLOSED; /* CLOSED or OPEN */
881 ti->sap_status = CLOSED; /* CLOSED or OPEN */
882 ti->open_failure = NO; /* NO or YES */
883 ti->open_mode = MANUAL; /* MANUAL or AUTOMATIC */
885 ti->sram_phys &= ~1; /* to reverse what we do in tok_close */
887 spin_lock_init(&ti->lock);
888 init_timer(&ti->tr_timer);
895 i= interruptible_sleep_on_timeout(&ti->wait_for_reset, 25 * HZ);
899 if (ti->open_status == OPEN && ti->sap_status==OPEN) {
927 struct tok_info *ti;
930 ti = (struct tok_info *) dev->priv;
931 SET_PAGE(ti->init_srb_page);
932 writeb(~SRB_RESP_INT, ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_ODD);
934 writeb(0, ti->init_srb + i);
935 writeb(DIR_OPEN_ADAPTER, ti->init_srb + COMMAND_OFST);
936 writew(htons(OPEN_PASS_BCON_MAC), ti->init_srb + OPEN_OPTIONS_OFST);
937 if (ti->ring_speed == 16) {
938 writew(htons(ti->dhb_size16mb), ti->init_srb + DHB_LENGTH_OFST);
939 writew(htons(ti->rbuf_cnt16), ti->init_srb + NUM_RCV_BUF_OFST);
940 writew(htons(ti->rbuf_len16), ti->init_srb + RCV_BUF_LEN_OFST);
942 writew(htons(ti->dhb_size4mb), ti->init_srb + DHB_LENGTH_OFST);
943 writew(htons(ti->rbuf_cnt4), ti->init_srb + NUM_RCV_BUF_OFST);
944 writew(htons(ti->rbuf_len4), ti->init_srb + RCV_BUF_LEN_OFST);
946 writeb(NUM_DHB, /* always 2 */ ti->init_srb + NUM_DHB_OFST);
947 writeb(DLC_MAX_SAP, ti->init_srb + DLC_MAX_SAP_OFST);
948 writeb(DLC_MAX_STA, ti->init_srb + DLC_MAX_STA_OFST);
949 ti->srb = ti->init_srb; /* We use this one in the interrupt handler */
950 ti->srb_page = ti->init_srb_page;
952 readb(ti->init_srb + NUM_DHB_OFST),
953 ntohs(readw(ti->init_srb + DHB_LENGTH_OFST)),
954 ntohs(readw(ti->init_srb + NUM_RCV_BUF_OFST)),
955 ntohs(readw(ti->init_srb + RCV_BUF_LEN_OFST)));
956 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
957 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
965 struct tok_info *ti = (struct tok_info *) dev->priv;
967 SET_PAGE(ti->srb_page);
969 writeb(0, ti->srb + i);
976 writeb(DLC_OPEN_SAP, ti->srb + COMMAND_OFST);
977 writew(htons(MAX_I_FIELD), ti->srb + MAX_I_FIELD_OFST);
978 writeb(SAP_OPEN_IND_SAP | SAP_OPEN_PRIORITY, ti->srb+ SAP_OPTIONS_OFST);
979 writeb(SAP_OPEN_STATION_CNT, ti->srb + STATION_COUNT_OFST);
980 writeb(type, ti->srb + SAP_VALUE_OFST);
981 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
989 struct tok_info *ti = (struct tok_info *) dev->priv;
997 if (/*BMSHELPdev->start == 0 ||*/ ti->open_status != OPEN) return;
1007 SET_PAGE(ti->srb_page);
1009 writeb(0, ti->srb + i);
1013 writeb(DIR_SET_FUNC_ADDR, ti->srb + COMMAND_OFST);
1015 writeb(address[i], ti->srb + FUNCT_ADDRESS_OFST + i);
1016 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1030 struct tok_info *ti;
1032 ti = (struct tok_info *) dev->priv;
1037 spin_lock_irqsave(&(ti->lock), flags);
1040 ti->current_skb = skb;
1041 SET_PAGE(ti->srb_page);
1042 writeb(XMIT_UI_FRAME, ti->srb + COMMAND_OFST);
1043 writew(ti->exsap_station_id, ti->srb + STATION_ID_OFST);
1044 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1045 spin_unlock_irqrestore(&(ti->lock), flags);
1054 struct tok_info *ti = (struct tok_info *) dev->priv;
1058 del_timer_sync(&ti->tr_timer);
1060 ti->sram_phys |= 1;
1061 ti->open_status = CLOSED;
1086 static void __iomem *map_address(struct tok_info *ti, unsigned index, __u8 *page)
1088 if (ti->page_mask) {
1089 *page = (index >> 8) & ti->page_mask;
1090 index &= ~(ti->page_mask << 8);
1092 return ti->sram_virt + index;
1097 struct tok_info *ti = (struct tok_info *) dev->priv;
1101 ti->srb = map_address(ti,
1102 ntohs(readw(ti->init_srb + SRB_ADDRESS_OFST)),
1103 &ti->srb_page);
1104 ti->ssb = map_address(ti,
1105 ntohs(readw(ti->init_srb + SSB_ADDRESS_OFST)),
1106 &ti->ssb_page);
1107 ti->arb = map_address(ti,
1108 ntohs(readw(ti->init_srb + ARB_ADDRESS_OFST)),
1109 &ti->arb_page);
1110 ti->asb = map_address(ti,
1111 ntohs(readw(ti->init_srb + ASB_ADDRESS_OFST)),
1112 &ti->asb_page);
1113 ti->current_skb = NULL;
1114 ret_code = readb(ti->init_srb + RETCODE_OFST);
1115 err = ntohs(readw(ti->init_srb + OPEN_ERROR_CODE_OFST));
1117 ti->open_status = OPEN; /* TR adapter is now available */
1118 if (ti->open_mode == AUTOMATIC) {
1121 writeb(~SRB_RESP_INT, ti->mmio+ACA_OFFSET+ACA_RESET+ISRP_ODD);
1125 ti->open_failure = YES;
1128 if (!ti->auto_speedsave) {
1132 ti->open_action = FAIL;
1154 if (ti->open_action != FAIL) {
1155 if (ti->open_mode==AUTOMATIC){
1156 ti->open_action = REOPEN;
1157 ibmtr_reset_timer(&(ti->tr_timer), dev);
1160 wake_up(&ti->wait_for_reset);
1172 struct tok_info *ti;
1182 ti = (struct tok_info *) dev->priv;
1183 if (ti->sram_phys & 1)
1185 spin_lock(&(ti->lock));
1187 save_srpr = readb(ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1191 writeb((~INT_ENABLE), ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_EVEN);
1194 if (ti->adapter_int_enable)
1195 outb(0, ti->adapter_int_enable);
1197 outb(0, ti->global_int_enable);
1198 if (ti->do_tok_int == FIRST_INT){
1201 writeb(save_srpr, ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1203 spin_unlock(&(ti->lock));
1208 status = readb(ti->mmio + ACA_OFFSET + ACA_RW + ISRP_ODD);
1209 /*BMSstatus_even = readb (ti->mmio + ACA_OFFSET + ACA_RW + ISRP_EVEN) */
1217 check_reason = map_address(ti,
1218 ntohs(readw(ti->mmio+ ACA_OFFSET+ACA_RW + WWCR_EVEN)),
1227 writeb(~ADAP_CHK_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1228 status = readb(ti->mmio + ACA_OFFSET + ACA_RW + ISRA_EVEN);
1230 ti->open_status = CLOSED;
1231 ti->sap_status = CLOSED;
1232 ti->open_mode = AUTOMATIC;
1235 ti->open_action = RESTART;
1237 ibmtr_reset_timer(&(ti->tr_timer), dev);/*BMS try to reopen*/
1238 spin_unlock(&(ti->lock));
1241 if (readb(ti->mmio + ACA_OFFSET + ACA_RW + ISRP_EVEN)
1244 (int)readb(ti->mmio+ ACA_OFFSET + ACA_RW + ISRP_EVEN));
1246 ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_EVEN);
1247 status= readb(ti->mmio+ ACA_OFFSET + ACA_RW + ISRA_EVEN);/*BMS*/
1249 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1251 writeb(save_srpr, ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1253 spin_unlock(&(ti->lock));
1257 SET_PAGE(ti->srb_page);
1260 readb(ti->srb), readb(ti->srb + RETCODE_OFST));
1262 switch (readb(ti->srb)) { /* SRB command check */
1265 xmit_ret_code = readb(ti->srb + RETCODE_OFST);
1269 if (ti->current_skb) {
1270 dev_kfree_skb_irq(ti->current_skb);
1271 ti->current_skb = NULL;
1275 if (ti->readlog_pending)
1282 xmit_ret_code = readb(ti->srb + RETCODE_OFST);
1286 if (ti->current_skb) {
1287 dev_kfree_skb_irq(ti->current_skb);
1288 ti->current_skb = NULL;
1291 if (ti->readlog_pending)
1299 if (readb(ti->srb + RETCODE_OFST)) {
1302 (int) readb(ti->srb + RETCODE_OFST));
1303 ti->open_action = REOPEN;
1304 ibmtr_reset_timer(&(ti->tr_timer), dev);
1307 ti->exsap_station_id = readw(ti->srb + STATION_ID_OFST);
1308 ti->sap_status = OPEN;/* TR adapter is now available */
1309 if (ti->open_mode==MANUAL){
1310 wake_up(&ti->wait_for_reset);
1321 if (readb(ti->srb + RETCODE_OFST))
1323 (int) readb(ti->srb + COMMAND_OFST),
1324 (int) readb(ti->srb + RETCODE_OFST));
1327 if (readb(ti->srb + RETCODE_OFST)){
1329 (int) readb(ti->srb + RETCODE_OFST));
1352 (int) readb(ti->srb + LINE_ERRORS_OFST),
1353 (int) readb(ti->srb + INTERNAL_ERRORS_OFST),
1354 (int) readb(ti->srb + BURST_ERRORS_OFST),
1355 (int) readb(ti->srb + AC_ERRORS_OFST),
1356 (int) readb(ti->srb + ABORT_DELIMITERS_OFST),
1357 (int) readb(ti->srb + LOST_FRAMES_OFST),
1358 (int) readb(ti->srb + RECV_CONGEST_COUNT_OFST),
1359 (int) readb(ti->srb + FRAME_COPIED_ERRORS_OFST),
1360 (int) readb(ti->srb + FREQUENCY_ERRORS_OFST),
1361 (int) readb(ti->srb + TOKEN_ERRORS_OFST));
1367 (int) readb(ti->srb));
1369 writeb(~SRB_RESP_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1372 SET_PAGE(ti->asb_page);
1374 DPRINTK("ASB resp: cmd=%02X\n", readb(ti->asb));
1377 switch (readb(ti->asb)) { /* ASB command check */
1384 (int) readb(ti->asb));
1386 if (readb(ti->asb + 2) != 0xff) /* checks ret_code */
1388 (int) readb(ti->asb + 2), (int) readb(ti->asb));
1389 writeb(~ASB_FREE_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1396 SET_PAGE(ti->arb_page);
1398 DPRINTK("ARB resp: cmd=%02X\n", readb(ti->arb));
1401 switch (readb(ti->arb)) { /* ARB command check */
1404 ntohs(readw(ti->arb + STATUS_OFST)),
1405 ntohs(readw(ti->arb+ STATION_ID_OFST)));
1412 ring_status= ntohs(readw(ti->arb + NETW_STATUS_OFST));
1428 ti->open_mode = AUTOMATIC;
1429 ti->open_status = CLOSED; /*12/2000 BMS*/
1430 ti->open_action = REOPEN;
1431 ibmtr_reset_timer(&(ti->tr_timer), dev);
1434 ti->readlog_pending = 1;
1445 (int) readb(ti->arb));
1448 writeb(~ARB_CMD_INT, ti->mmio+ ACA_OFFSET+ACA_RESET + ISRP_ODD);
1449 writeb(ARB_FREE, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1453 SET_PAGE(ti->ssb_page);
1456 readb(ti->ssb), readb(ti->ssb + 2));
1459 switch (readb(ti->ssb)) { /* SSB command check */
1462 retcode = readb(ti->ssb + 2);
1466 (int)retcode, (int)readb(ti->ssb + 6));
1468 ti->tr_stats.tx_packets++;
1472 (int) readb(ti->ssb + 2));
1475 (int) readb(ti->ssb));
1477 writeb(~SSB_RESP_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1478 writeb(SSB_FREE, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1481 writeb(save_srpr, ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1483 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1484 spin_unlock(&(ti->lock));
1498 struct tok_info *ti;
1501 ti = (struct tok_info *) dev->priv;
1503 ti->do_tok_int = NOT_FIRST;
1506 writeb(ti->sram_base, ti->mmio + ACA_OFFSET + ACA_RW + RRR_EVEN);
1508 ti->sram_virt = ioremap(((__u32)ti->sram_base << 12), ti->avail_shared_ram);
1510 ti->init_srb = map_address(ti,
1511 ntohs(readw(ti->mmio + ACA_OFFSET + WRBR_EVEN)),
1512 &ti->init_srb_page);
1513 if (ti->page_mask && ti->avail_shared_ram == 127) {
1517 last_512 = map_address(ti, 0xfe00, &last_512_page);
1523 SET_PAGE(ti->init_srb_page);
1529 DPRINTK("ti->init_srb_page=0x%x\n", ti->init_srb_page);
1530 DPRINTK("init_srb(%p):", ti->init_srb );
1532 printk("%02X ", (int) readb(ti->init_srb + i));
1537 hw_encoded_addr = readw(ti->init_srb + ENCODED_ADDRESS_OFST);
1540 readb(ti->init_srb+offsetof(struct srb_init_response,init_status));
1542 ti->ring_speed = init_status & 0x01 ? 16 : 4;
1544 ti->ring_speed, (unsigned int)dev->mem_start);
1545 ti->auto_speedsave=readb(ti->init_srb+INIT_STATUS_2_OFST)&4?TRUE:FALSE;
1547 if (ti->open_mode == MANUAL) wake_up(&ti->wait_for_reset);
1563 struct tok_info *ti = (struct tok_info *) dev->priv;
1564 struct trh_hdr *trhdr = (struct trh_hdr *) ti->current_skb->data;
1575 SET_PAGE(ti->asb_page);
1577 if (readb(ti->asb+RETCODE_OFST) != 0xFF) DPRINTK("ASB not free !!!\n");
1583 SET_PAGE(ti->arb_page);
1584 dhb=dhb_base=ntohs(readw(ti->arb + DHB_ADDRESS_OFST));
1585 if (ti->page_mask) {
1586 dhb_page = (dhb_base >> 8) & ti->page_mask;
1587 dhb=dhb_base & ~(ti->page_mask << 8);
1589 dhbuf = ti->sram_virt + dhb;
1598 llc = (struct trllc *) (ti->current_skb->data + hdr_len);
1601 SET_PAGE(ti->srb_page);
1602 memcpy_fromio(&xsrb, ti->srb, sizeof(xsrb));
1603 SET_PAGE(ti->asb_page);
1606 writeb(xmit_command, ti->asb + COMMAND_OFST);
1607 writew(xsrb.station_id, ti->asb + STATION_ID_OFST);
1608 writeb(llc_ssap, ti->asb + RSAP_VALUE_OFST);
1609 writeb(xsrb.cmd_corr, ti->asb + CMD_CORRELATE_OFST);
1610 writeb(0, ti->asb + RETCODE_OFST);
1612 writew(htons(0x11), ti->asb + FRAME_LENGTH_OFST);
1613 writeb(0x0e, ti->asb + HEADER_LENGTH_OFST);
1621 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1628 writeb(hdr_len, ti->asb + HEADER_LENGTH_OFST);
1629 writew(htons(ti->current_skb->len), ti->asb + FRAME_LENGTH_OFST);
1630 src_len=ti->current_skb->len;
1634 if (ti->page_mask) {
1635 dhb_page=(dhb >> 8) & ti->page_mask;
1636 dhb=dhb & ~(ti->page_mask << 8);
1639 dhbuf = ti->sram_virt + dhb;
1642 memcpy_toio(dhbuf,&ti->current_skb->data[src_offset],
1650 memcpy_toio(dhbuf, &ti->current_skb->data[src_offset], src_len);
1653 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1654 ti->tr_stats.tx_bytes += ti->current_skb->len;
1655 dev_kfree_skb_irq(ti->current_skb);
1656 ti->current_skb = NULL;
1658 if (ti->readlog_pending)
1677 struct tok_info *ti = (struct tok_info *) dev->priv;
1691 SET_PAGE(ti->arb_page);
1692 memcpy_fromio(&rarb, ti->arb, sizeof(rarb));
1694 rbuf = map_address(ti, rbuffer, &rbuffer_page);
1696 SET_PAGE(ti->asb_page);
1698 if (readb(ti->asb + RETCODE_OFST) !=0xFF) DPRINTK("ASB not free !!!\n");
1700 writeb(REC_DATA, ti->asb + COMMAND_OFST);
1701 writew(rarb.station_id, ti->asb + STATION_ID_OFST);
1702 writew(rarb.rec_buf_addr, ti->asb + RECEIVE_BUFFER_OFST);
1709 dlc_hdr_len = readb(ti->arb + DLC_HDR_LENGTH_OFST);
1728 SET_PAGE(ti->asb_page);
1729 writeb(DATA_LOST, ti->asb + RETCODE_OFST);
1730 ti->tr_stats.rx_dropped++;
1731 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1765 ti->tr_stats.rx_dropped++;
1766 SET_PAGE(ti->asb_page);
1767 writeb(DATA_LOST, ti->asb + offsetof(struct asb_rec, ret_code));
1768 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1810 rbuf = map_address(ti, rbuffer, &rbuffer_page);
1816 SET_PAGE(ti->asb_page);
1817 writeb(0, ti->asb + offsetof(struct asb_rec, ret_code));
1819 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1821 ti->tr_stats.rx_bytes += skb->len;
1822 ti->tr_stats.rx_packets++;
1849 struct tok_info *ti = (struct tok_info *) dev->priv;
1851 if ( ti->open_action == RESTART){
1852 ti->do_tok_int = FIRST_INT;
1855 if (ti->page_mask)
1857 ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1860 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1869 struct tok_info *ti;
1871 ti = (struct tok_info *) dev->priv;
1873 ti->readlog_pending = 0;
1874 SET_PAGE(ti->srb_page);
1875 writeb(DIR_READ_LOG, ti->srb);
1876 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1877 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1902 struct tok_info *ti = (struct tok_info *) dev->priv;
1904 if (ti->ring_speed == 16 && mtu > ti->maxmtu16)
1906 if (ti->ring_speed == 4 && mtu > ti->maxmtu4)