Lines Matching refs:hw
154 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
163 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
168 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
172 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
176 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
180 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
181 *val = gma_read16(hw, port, GM_SMI_DATA);
191 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
195 if (__gm_phy_read(hw, port, reg, &v) != 0)
196 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
201 static void sky2_power_on(struct sky2_hw *hw)
204 sky2_write8(hw, B0_POWER_CTRL,
208 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
210 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
212 sky2_write8(hw, B2_Y2_CLK_GATE,
217 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
219 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
222 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
223 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
225 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
226 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
230 static void sky2_power_aux(struct sky2_hw *hw)
232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
233 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
236 sky2_write8(hw, B2_Y2_CLK_GATE,
242 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
243 sky2_write8(hw, B0_POWER_CTRL,
248 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
253 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
255 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
257 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
258 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
259 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
260 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
262 reg = gma_read16(hw, port, GM_RX_CTRL);
264 gma_write16(hw, port, GM_RX_CTRL, reg);
292 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
294 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
298 && !(hw->chip_id == CHIP_ID_YUKON_XL
299 || hw->chip_id == CHIP_ID_YUKON_EC_U
300 || hw->chip_id == CHIP_ID_YUKON_EX)) {
301 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
308 if (hw->chip_id == CHIP_ID_YUKON_EC)
315 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
318 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
319 if (sky2_is_copper(hw)) {
320 if (hw->chip_id == CHIP_ID_YUKON_FE) {
332 && (hw->chip_id == CHIP_ID_YUKON_XL
333 || hw->chip_id == CHIP_ID_YUKON_EC_U
334 || hw->chip_id == CHIP_ID_YUKON_EX)) {
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
349 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
350 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
353 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
354 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
357 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
359 if (hw->pmd_type == 'P') {
361 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
364 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
366 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
369 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
378 if (sky2_is_copper(hw)) {
433 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
435 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
438 gma_write16(hw, port, GM_GP_CTRL, reg);
440 if (hw->chip_id != CHIP_ID_YUKON_FE)
441 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
443 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
444 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
450 switch (hw->chip_id) {
455 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
461 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
465 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
468 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
471 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
478 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
487 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
492 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
495 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
498 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
505 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
508 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
518 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
519 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
521 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
524 gm_phy_write(hw, port, 0x18, 0xaa99);
525 gm_phy_write(hw, port, 0x17, 0x2011);
528 gm_phy_write(hw, port, 0x18, 0xa204);
529 gm_phy_write(hw, port, 0x17, 0x2002);
532 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
533 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
534 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
542 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
548 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
550 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
553 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
560 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
563 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
564 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
571 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
572 sky2_pci_read32(hw, PCI_DEV_REG1);
573 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
581 sky2_phy_init(sky2->hw, sky2->port);
588 struct sky2_hw *hw = sky2->hw;
595 sky2_write16(hw, B0_CTST, CS_RST_CLR);
596 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
598 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
599 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
609 sky2_phy_power(hw, port, 1);
616 gma_write16(hw, port, GM_GP_CTRL,
621 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
625 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
638 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
641 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
642 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
644 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
645 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
648 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
652 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
654 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
657 const u8 *addr = hw->dev[port]->dev_addr;
659 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
660 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
662 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
664 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
667 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
669 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
670 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
671 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
672 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
673 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
676 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
679 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
682 sky2_phy_init(hw, port);
686 reg = gma_read16(hw, port, GM_PHY_ADDR);
687 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
690 gma_read16(hw, port, i);
691 gma_write16(hw, port, GM_PHY_ADDR, reg);
694 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
697 gma_write16(hw, port, GM_RX_CTRL,
701 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
704 gma_write16(hw, port, GM_TX_PARAM,
714 if (hw->dev[port]->mtu > ETH_DATA_LEN)
717 gma_write16(hw, port, GM_SERIAL_MODE, reg);
720 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
723 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
726 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
727 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
728 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
731 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
732 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
736 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
738 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
741 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
742 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
744 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
745 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
746 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
749 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
752 if (hw->dev[port]->mtu > ETH_DATA_LEN)
753 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
756 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
763 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
767 /* convert from K bytes to qwords used for hw register */
772 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
773 sky2_write32(hw, RB_ADDR(q, RB_START), start);
774 sky2_write32(hw, RB_ADDR(q, RB_END), end);
775 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
776 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
785 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
786 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
789 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
790 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
795 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
798 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
799 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
803 static void sky2_qset(struct sky2_hw *hw, u16 q)
805 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
806 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
807 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
808 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
814 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
817 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
818 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
819 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
820 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
821 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
822 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
824 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
843 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
847 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
945 sky2_write32(sky2->hw,
963 struct sky2_hw *hw = sky2->hw;
968 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
971 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
972 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
978 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
981 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
995 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1007 struct sky2_hw *hw = sky2->hw;
1022 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1034 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1046 struct sky2_hw *hw = sky2->hw;
1050 netif_poll_disable(sky2->hw->dev[0]);
1054 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1056 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1059 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1061 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1065 netif_poll_enable(sky2->hw->dev[0]);
1118 struct sky2_hw *hw = sky2->hw;
1124 sky2_qset(hw, rxq);
1127 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1128 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1132 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1133 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1134 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1135 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1137 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1180 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1185 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1187 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1188 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1192 sky2_put_idx(hw, rxq, sky2->rx_put);
1203 struct sky2_hw *hw = sky2->hw;
1207 struct net_device *otherdev = hw->dev[sky2->port^1];
1214 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1218 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1220 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1230 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1243 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1254 sky2_phy_power(hw, port, 1);
1256 sky2_mac_init(hw, port);
1259 ramsize = sky2_read8(hw, B2_E_0) * 4;
1270 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1271 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1274 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1278 sky2_qset(hw, txqaddr[port]);
1281 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1282 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1283 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1285 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1293 imask = sky2_read32(hw, B0_IMSK);
1295 sky2_write32(hw, B0_IMSK, imask);
1301 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1306 pci_free_consistent(hw->pdev,
1357 struct sky2_hw *hw = sky2->hw;
1374 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1452 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1480 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1495 struct pci_dev *pdev = sky2->hw->pdev;
1554 struct sky2_hw *hw = sky2->hw;
1571 imask = sky2_read32(hw, B0_IMSK);
1573 sky2_write32(hw, B0_IMSK, imask);
1575 sky2_gmac_reset(hw, port);
1578 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1579 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1581 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1584 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1586 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1588 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1590 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1591 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1592 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1595 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1599 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1600 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1603 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1607 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1610 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1614 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1615 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1617 sky2_phy_power(hw, port, 0);
1620 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1622 synchronize_irq(hw->pdev->irq);
1627 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1631 pci_free_consistent(hw->pdev,
1645 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1647 if (!sky2_is_copper(hw))
1650 if (hw->chip_id == CHIP_ID_YUKON_FE)
1665 struct sky2_hw *hw = sky2->hw;
1676 reg = gma_read16(hw, port, GM_GP_CTRL);
1678 gma_write16(hw, port, GM_GP_CTRL, reg);
1680 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1686 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1689 if (hw->chip_id == CHIP_ID_YUKON_XL
1690 || hw->chip_id == CHIP_ID_YUKON_EC_U
1691 || hw->chip_id == CHIP_ID_YUKON_EX) {
1692 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1709 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1710 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1711 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1724 struct sky2_hw *hw = sky2->hw;
1728 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1730 reg = gma_read16(hw, port, GM_GP_CTRL);
1732 gma_write16(hw, port, GM_GP_CTRL, reg);
1738 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1743 sky2_phy_init(hw, port);
1756 struct sky2_hw *hw = sky2->hw;
1760 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1761 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1773 sky2->speed = sky2_phy_speed(hw, aux);
1779 if (!sky2_is_copper(hw)) {
1806 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1810 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1818 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1820 struct net_device *dev = hw->dev[port];
1828 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1829 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1842 sky2->speed = sky2_phy_speed(hw, phystat);
1864 struct sky2_hw *hw = sky2->hw;
1871 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1872 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1875 schedule_work(&hw->restart_work);
1881 struct sky2_hw *hw = sky2->hw;
1890 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1898 imask = sky2_read32(hw, B0_IMSK);
1899 sky2_write32(hw, B0_IMSK, 0);
1903 netif_poll_disable(hw->dev[0]);
1905 synchronize_irq(hw->pdev->irq);
1907 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
1909 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1913 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1917 ctl = gma_read16(hw, port, GM_GP_CTRL);
1918 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1930 gma_write16(hw, port, GM_SERIAL_MODE, mode);
1932 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
1935 sky2_write32(hw, B0_IMSK, imask);
1940 gma_write16(hw, port, GM_GP_CTRL, ctl);
1942 netif_poll_enable(hw->dev[0]);
1959 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1964 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2021 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2025 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2101 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2106 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2110 while (hw->st_idx != hwidx) {
2111 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2117 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2120 dev = hw->dev[le->link];
2151 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
2187 sky2_write32(sky2->hw,
2196 sky2_tx_done(hw->dev[0], status & 0xfff);
2197 if (hw->dev[1])
2198 sky2_tx_done(hw->dev[1],
2212 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2217 sky2 = netdev_priv(hw->dev[0]);
2218 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2222 sky2 = netdev_priv(hw->dev[1]);
2223 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2229 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2231 struct net_device *dev = hw->dev[port];
2234 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2242 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2250 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2256 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2262 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2269 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2273 static void sky2_hw_intr(struct sky2_hw *hw)
2275 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2278 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2283 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2285 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2288 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2289 sky2_pci_write16(hw, PCI_STATUS,
2291 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2298 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2301 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2305 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2306 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2308 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2311 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2313 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2318 sky2_hw_error(hw, 0, status);
2321 sky2_hw_error(hw, 1, status);
2324 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2326 struct net_device *dev = hw->dev[port];
2328 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2335 gma_read16(hw, port, GM_RX_IRQ_SRC);
2338 gma_read16(hw, port, GM_TX_IRQ_SRC);
2342 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2347 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2352 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2355 struct net_device *dev = hw->dev[port];
2361 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2364 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2366 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2369 static inline void sky2_idle_start(struct sky2_hw *hw)
2372 mod_timer(&hw->idle_timer,
2378 struct sky2_hw *hw = (struct sky2_hw *) arg;
2379 struct net_device *dev = hw->dev[0];
2384 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2388 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2391 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2394 sky2_hw_intr(hw);
2397 sky2_mac_intr(hw, 0);
2400 sky2_mac_intr(hw, 1);
2403 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2406 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2409 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2412 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2417 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2420 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2423 sky2_err_intr(hw, status);
2426 sky2_phy_intr(hw, 0);
2429 sky2_phy_intr(hw, 1);
2431 work_done = sky2_status_intr(hw, work_limit);
2436 sky2_read32(hw, B0_Y2_SP_LISR);
2447 struct sky2_hw *hw = dev_id;
2448 struct net_device *dev0 = hw->dev[0];
2452 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2456 prefetch(&hw->st_le[hw->st_idx]);
2467 struct net_device *dev0 = sky2->hw->dev[0];
2475 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2477 switch (hw->chip_id) {
2489 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2491 return sky2_mhz(hw) * us;
2494 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2496 return clk / sky2_mhz(hw);
2500 static int __devinit sky2_init(struct sky2_hw *hw)
2504 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2506 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2507 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2508 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2509 hw->chip_id);
2513 if (hw->chip_id == CHIP_ID_YUKON_EX)
2514 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2518 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2519 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2521 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2524 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2525 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2526 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2527 hw->chip_id, hw->chip_rev);
2531 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2532 hw->ports = 1;
2533 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2535 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2536 ++hw->ports;
2542 static void sky2_reset(struct sky2_hw *hw)
2548 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2549 status = sky2_read16(hw, HCU_CCSR);
2552 sky2_write16(hw, HCU_CCSR, status);
2554 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2555 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2558 sky2_write8(hw, B0_CTST, CS_RST_SET);
2559 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2562 status = sky2_pci_read16(hw, PCI_STATUS);
2564 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2565 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2568 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2571 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2572 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2575 sky2_power_on(hw);
2577 for (i = 0; i < hw->ports; i++) {
2578 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2579 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2582 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2585 sky2_write32(hw, B2_I2C_IRQ, 1);
2588 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2589 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2591 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2594 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2597 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2598 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2601 for (i = 0; i < hw->ports; i++)
2602 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2605 for (i = 0; i < hw->ports; i++) {
2606 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2608 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2609 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2610 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2611 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2612 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2613 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2614 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2615 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2616 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2617 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2618 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2619 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2622 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2624 for (i = 0; i < hw->ports; i++)
2625 sky2_gmac_reset(hw, i);
2627 memset(hw->st_le, 0, STATUS_LE_BYTES);
2628 hw->st_idx = 0;
2630 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2631 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2633 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2634 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2637 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2639 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2640 sky2_write8(hw, STAT_FIFO_WM, 16);
2643 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2644 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2646 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2648 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2649 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2650 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2653 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2655 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2656 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2657 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2662 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2666 dev_dbg(&hw->pdev->dev, "restarting\n");
2668 del_timer_sync(&hw->idle_timer);
2671 sky2_write32(hw, B0_IMSK, 0);
2672 sky2_read32(hw, B0_IMSK);
2674 netif_poll_disable(hw->dev[0]);
2676 for (i = 0; i < hw->ports; i++) {
2677 dev = hw->dev[i];
2682 sky2_reset(hw);
2683 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2684 netif_poll_enable(hw->dev[0]);
2686 for (i = 0; i < hw->ports; i++) {
2687 dev = hw->dev[i];
2698 sky2_idle_start(hw);
2703 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2705 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2712 wol->supported = sky2_wol_supported(sky2->hw);
2719 struct sky2_hw *hw = sky2->hw;
2721 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2726 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2727 sky2_write32(hw, B0_CTST, sky2->wol
2735 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2737 if (sky2_is_copper(hw)) {
2744 if (hw->chip_id != CHIP_ID_YUKON_FE)
2758 struct sky2_hw *hw = sky2->hw;
2761 ecmd->supported = sky2_supported_modes(hw);
2763 if (sky2_is_copper(hw)) {
2787 const struct sky2_hw *hw = sky2->hw;
2788 u32 supported = sky2_supported_modes(hw);
2851 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2911 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2937 struct sky2_hw *hw = sky2->hw;
2941 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2942 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2943 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2944 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2947 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2991 struct sky2_hw *hw = sky2->hw;
2999 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3001 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3005 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3008 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3024 struct sky2_hw *hw = sky2->hw;
3035 reg = gma_read16(hw, port, GM_RX_CTRL);
3055 gma_write16(hw, port, GM_MC_ADDR_H1,
3057 gma_write16(hw, port, GM_MC_ADDR_H2,
3059 gma_write16(hw, port, GM_MC_ADDR_H3,
3061 gma_write16(hw, port, GM_MC_ADDR_H4,
3064 gma_write16(hw, port, GM_RX_CTRL, reg);
3070 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3074 switch (hw->chip_id) {
3076 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3077 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3078 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3085 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3089 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3090 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3099 struct sky2_hw *hw = sky2->hw;
3113 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3114 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3115 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3116 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3117 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3119 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3120 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3125 sky2_led(hw, port, onoff);
3136 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3137 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3138 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3139 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3140 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3142 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3143 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3190 struct sky2_hw *hw = sky2->hw;
3192 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3195 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3196 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3198 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3200 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3203 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3204 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3206 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3208 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3211 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3212 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3215 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3225 struct sky2_hw *hw = sky2->hw;
3226 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3241 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3243 sky2_write32(hw, STAT_TX_TIMER_INI,
3244 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3245 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3247 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3250 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3252 sky2_write32(hw, STAT_LEV_TIMER_INI,
3253 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3254 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3256 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3259 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3261 sky2_write32(hw, STAT_ISR_TIMER_INI,
3262 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3263 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3265 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3327 const void __iomem *io = sky2->hw->regs;
3346 const struct sky2_hw *hw = sky2->hw;
3349 (hw->chip_id == CHIP_ID_YUKON_EX
3350 || hw->chip_id == CHIP_ID_YUKON_EC_U);
3404 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3412 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3417 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3418 dev->irq = hw->pdev->irq;
3443 sky2->hw = hw;
3452 sky2->advertising = sky2_supported_modes(hw);
3460 hw->dev[port] = dev;
3474 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3498 struct sky2_hw *hw = dev_id;
3499 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3505 hw->msi = 1;
3506 wake_up(&hw->msi_wait);
3507 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3509 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3515 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3517 struct pci_dev *pdev = hw->pdev;
3520 init_waitqueue_head (&hw->msi_wait);
3522 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3524 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3530 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3531 sky2_read8(hw, B0_CTST);
3533 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3535 if (!hw->msi) {
3541 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3544 sky2_write32(hw, B0_IMSK, 0);
3545 sky2_read32(hw, B0_IMSK);
3547 free_irq(pdev->irq, hw);
3568 struct sky2_hw *hw;
3605 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3606 if (!hw) {
3611 hw->pdev = pdev;
3613 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3614 if (!hw->regs) {
3625 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3627 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3632 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3633 &hw->st_dma);
3634 if (!hw->st_le)
3637 err = sky2_init(hw);
3643 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3644 hw->chip_id, hw->chip_rev);
3646 sky2_reset(hw);
3648 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
3655 err = sky2_test_msi(hw);
3668 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3669 dev->name, hw);
3674 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3678 if (hw->ports > 1) {
3681 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
3687 hw->dev[1] = NULL;
3693 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3694 INIT_WORK(&hw->restart_work, sky2_restart);
3696 sky2_idle_start(hw);
3698 pci_set_drvdata(pdev, hw);
3703 if (hw->msi)
3709 sky2_write8(hw, B0_CTST, CS_RST_SET);
3710 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3712 iounmap(hw->regs);
3714 kfree(hw);
3726 struct sky2_hw *hw = pci_get_drvdata(pdev);
3729 if (!hw)
3732 del_timer_sync(&hw->idle_timer);
3736 sky2_write32(hw, B0_IMSK, 0);
3737 synchronize_irq(hw->pdev->irq);
3739 dev0 = hw->dev[0];
3740 dev1 = hw->dev[1];
3745 sky2_power_aux(hw);
3747 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3748 sky2_write8(hw, B0_CTST, CS_RST_SET);
3749 sky2_read8(hw, B0_CTST);
3751 free_irq(pdev->irq, hw);
3752 if (hw->msi)
3754 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3761 iounmap(hw->regs);
3762 kfree(hw);
3770 struct sky2_hw *hw = pci_get_drvdata(pdev);
3773 if (!hw)
3776 del_timer_sync(&hw->idle_timer);
3777 netif_poll_disable(hw->dev[0]);
3779 for (i = 0; i < hw->ports; i++) {
3780 struct net_device *dev = hw->dev[i];
3792 sky2_write32(hw, B0_IMSK, 0);
3793 sky2_power_aux(hw);
3804 struct sky2_hw *hw = pci_get_drvdata(pdev);
3807 if (!hw)
3821 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3822 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3824 sky2_reset(hw);
3826 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3828 for (i = 0; i < hw->ports; i++) {
3829 struct net_device *dev = hw->dev[i];
3841 netif_poll_enable(hw->dev[0]);
3842 sky2_idle_start(hw);
3853 struct sky2_hw *hw = pci_get_drvdata(pdev);
3856 if (!hw)
3859 del_timer_sync(&hw->idle_timer);
3860 netif_poll_disable(hw->dev[0]);
3862 for (i = 0; i < hw->ports; i++) {
3863 struct net_device *dev = hw->dev[i];
3873 sky2_power_aux(hw);