Lines Matching refs:smc
27 #define ADDR(a) ((a)+smc->hw.iop)
28 #define ADDRS(smc,a) ((a)+(smc)->hw.iop)
112 #define FM_A(a) (FMA(a)+smc->hw.iop) /* FORMAC Plus physical addr */
113 #define P1_A(a) (P1A(a)+smc->hw.iop) /* PLC1 (r/w) */
114 #define P2_A(a) (P2A(a)+smc->hw.iop) /* PLC2 (r/w) */
115 #define TI_A(a) (TIA(a)+smc->hw.iop) /* Timer (r/w) */
116 #define PR_A(a) (PRA(a)+smc->hw.iop) /* config. PROM */
117 #define C0_A(a) (C0A(a)+smc->hw.iop) /* config. RAM */
118 #define C1_A(a) (C1A(a)+smc->hw.iop) /* config. RAM */
119 #define C2_A(a) (C2A(a)+smc->hw.iop) /* config. RAM */
131 #define CSR_A (CSRA+smc->hw.iop) /* control/status register address (r/w) */
133 #define CSR_AS(smc) (CSRA+(smc)->hw.iop) /* control/status register address (r/w) */
135 #define ISR_A (ISRA+smc->hw.iop) /* int. source register address (upper 8Bits) */
136 #define PLC1_I (PLC1I+smc->hw.iop) /* clear PLC1 internupt (write only) */
137 #define PLC2_I (PLC2I+smc->hw.iop) /* clear PLC2 interrupt (write only) */
138 #define CSF_A (CSFA+smc->hw.iop) /* control/status FIFO BUSY flags (r/w) */
139 #define RQA_A (RQAA+smc->hw.iop) /* Request reg. (write only) */
140 #define WCT_A (WCTA+smc->hw.iop) /* word counter (r/w) */
141 #define FFLAG_A (FFLAG+smc->hw.iop) /* FLAG/V_FULL (FIFO almost full, write only)*/
220 if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
224 if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
229 if (!k) SMT_PANIC(smc,HWM_E0019,HWM_E0019_MSG) ; }
233 if (!k) SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ; }
241 (CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|smc->hw.led)
244 (CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|smc->hw.led)
247 #define CLI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))&\
248 (CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|(smc)->hw.led)
253 (CS_CRESET|CS_BYPASS|CS_RESET_FIFO))|CS_IMSK|smc->hw.led)
255 #define STI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))&\
256 (CS_CRESET|CS_BYPASS|CS_RESET_FIFO))|CS_IMSK|(smc)->hw.led)
598 #define VPP_ON() if (smc->hw.rev == FM1_REV) { \
602 #define VPP_OFF() if (smc->hw.rev == FM1_REV) { \
624 SMT_PANIC(smc,HWM_E0020,HWM_E0020_MSG) ; \
626 SMT_PANIC(smc,HWM_E0014,HWM_E0014_MSG) ; \
634 if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
638 if (!k) SMT_PANIC(smc,HWM_E0019,HWM_E0019_MSG) ; }
645 if (!k) SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ; }
650 #define CLI_FBI(smc) outp(ADDRS((smc),IRQ_OTH_DIS),0)
663 #define STI_FBI(smc) outp(ADDRS((smc),IRQ_OTH_EN),0)
669 #define CLI_TCI(smc) outp(ADDRS((smc),IRQ_TC_DIS),0)
670 #define STI_TCI(smc) outp(ADDRS((smc),IRQ_TC_EN),0)
671 #define CHECK_TC(smc,k) {(k) = 10000 ;\
673 if (!k) SMT_PANIC(smc,HWM_E0018,HWM_E0018_MSG) ; }
699 #define FM_A(a) (FMA(a)+smc->hw.iop) /* FORMAC Plus physical addr */
700 #define PR_A(a) (PRA(a)+smc->hw.iop) /* PROM (read only)*/
701 #define P1_A(a) (P1A(a)+smc->hw.iop) /* PLC1 (r/w) */
702 #define P2_A(a) (P2A(a)+smc->hw.iop) /* PLC2 (r/w) */
703 #define TI_A(a) (TIA(a)+smc->hw.iop) /* Timer (r/w) */
705 #define ISR_A (0x0000+smc->hw.iop) /* int. source register address (read only) */
706 #define ACL_A (0x0000+smc->hw.iop) /* address counter low address (write only) */
707 #define ACH_A (0x0002+smc->hw.iop) /* address counter high address (write only)*/
708 #define TRC_A (0x0004+smc->hw.iop) /* transfer counter address (write only) */
709 #define PGR_A (0x0006+smc->hw.iop) /* page register address (write only) */
710 #define RQA_A (0x2000+smc->hw.iop) /* Request reg. (write only) */
711 #define CSR_A (0x3000+smc->hw.iop) /* control/status register address (r/w) */
713 #define CSR_AS(smc) (0x3000+(smc)->hw.iop) /* control/status register address */
715 #define PLC1_I (0x3400+smc->hw.iop) /* clear PLC1 interrupt bit */
716 #define PLC2_I (0x3800+smc->hw.iop) /* clear PLC2 interrupt bit */
789 #define CLI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))& \
797 #define STI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc)) & \
803 if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
1720 #define ADDR(a) (char far *) smc->hw.iop+(a)
1721 #define ADDRS(smc,a) (char far *) (smc)->hw.iop+(a)
1723 #define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \
1724 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
1725 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
1726 #define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \
1727 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
1728 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
1778 #define CLI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),0)
1782 #define STI_FBI() outpd(ADDR(B0_IMSK),smc->hw.is_imask)
1784 #define STI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask)
1788 #define STI_FBI_SMP(smc,iop) outpd((iop)+B0_IMSK,(smc)->hw.is_imask)